Browse Prior Art Database

A METHOD FOR SPEEDING-UP PROCESSOR BY USING PIPELINE REROUTING

IP.com Disclosure Number: IPCOM000016087D
Original Publication Date: 2002-Oct-19
Included in the Prior Art Database: 2003-Jun-21
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Abstract

Problem

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A METHOD FOR SPEEDING-UP PROCESSOR BY USING PIPELINE REROUTING

Problem

    Modern superscalar microprocessors use multiple-execution pipelines. In many cases, some of these pipelines are identical. For example, a processor may have two pipelines for execution of floating-point instruction. During the execution of an instruction, it may be forced to stay in a specific pipeline stage for a long period of time (more than a single cycle). This can delay the instructions that follow the initial instructions in the pipeline, since they cannot proceed to an occupied stage. Delays in the pipeline decrease the rate in which instructions are handled by the processor, and thus increases the execution time of programs.

    In many cases, instructions are stalled in a pipeline, even though the resources that are needed for their execution are available in another (identical) pipeline. In today's microprocessors, an instruction remains in the same pipeline it started in and waits for the pipeline stages to become available, even if similar stages in an equivalent pipeline are free.

Solution

    We propose an execution method for instructions that allows them to leave the pipeline in which they are currently executing and move to another, equivalent pipeline and continue their execution there. This allows the instructions to bypass the bottleneck that is created by an instruction that is forced to stay in a specific stage for a long time. Rerouting instructions between pipelines increases the utilization of the pipelines and increase the performance of the processor, without adding execution units.

    An instruction can be rerouted to a different pipeline only if the following conditions are met:

    The instruction can be executed in the new pipeline. For example, if pipeline A can execute add and divide commands and pipeline B can execute add and multiply commands, then add commands can be rerouted between the pipelines, while divide and multiply instructions cannot.

    The pipeline stage that the instruction is rerouted to will be free when the instruction arrives.

    The following diagram describes a possible use of the patent. The diagram shows two pipelines during the execution of a program. The instruction in stage 1C is delayed at this stage for a long period of time (e.g., performing a long operation, such as division). Therefore, the instruction in stage 1B cannot proceed to stage 1C. In current microprocessors, the instruction in stage 1B is stalled until the instruction in 1C continues to 1D and frees 1C. Using the new method, the instruction in 1B can be rerouted to pipeline 2 and continue its execution in stage 2C.

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Pipeline 1 Pipeline 2

1A

1B

2A

2B

Empty stage Occupied stage Long occupied stage

    To implement the invention, each stage of the pipe needs the following control signals:

    A signal indicating that the stage is ready to receive a new instruction in the next cycle (Ready)....