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Method to Provide and Protect Firmware Assisted Non-Maskable Interrupt Handlers (FWNMI) in a Computer System

IP.com Disclosure Number: IPCOM000016089D
Original Publication Date: 2002-Sep-23
Included in the Prior Art Database: 2003-Jun-21
Document File: 1 page(s) / 43K

Publishing Venue

IBM

Abstract

Method to Provide and Protect Firmware Assisted Non-Maskable Interrupt Handlers (FWNMI) in a Computer System Disclosed is a method to provide and protect Firmware Assisted Non-Maskable Interrupt (FWNMI) handlers in a computer system. Modern microprocessors will receive non-maskable interrupts (NMI). These interrupts can not be disabled or masked off, and must be handled whenever they occur. They are typically the System Reset Interrupt (SRI), and the system hardware error interrupt such as the Machine Check Interrupt (MCI). The Operating System (OS) normally handles these interrupts. However, between the time that a system is turned on until the OS is up and running to be able to handle these interrupts, the system firmware dynamically installs the firmware NMI First Level Interrupt Handlers (FLIH) during this time. Also, the firmware FLIH will be updated as needed, and will relinquish the vector spaces to the OS when the OS comes online. At different times in the execution of the system firmware, the firmware FLIHs will be relocated to the system firmware's protected working area. As long as the firmware FLIHs are present, any NMI will be handled in a seamless manner. This enhances Reliability, Availability, and Serviceability of the system. The installing/relocating process is outlined belows:

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  Method to Provide and Protect Firmware Assisted Non-Maskable Interrupt Handlers

(FWNMI) in a Computer System

Disclosed is a method to provide and protect Firmware Assisted Non-Maskable Interrupt (FWNMI) handlers in a computer system. Modern microprocessors will receive non-maskable interrupts (NMI). These interrupts can not be disabled or masked off, and must be handled whenever they occur. They are typically the System Reset Interrupt (SRI), and the system hardware error interrupt such as the Machine Check Interrupt (MCI). The Operating System (OS) normally handles these interrupts. However, between the time that a system is turned on until the OS is up and running to be able to handle these interrupts, the system firmware dynamically installs the firmware NMI First Level Interrupt Handlers (FLIH) during this time. Also, the firmware FLIH will be updated as needed, and will relinquish the vector spaces to the OS when the OS comes online.

At different times in the execution of the system firmware, the firmware FLIHs will be relocated to the system firmware's protected working area. As long as the firmware FLIHs are present, any NMI will be handled in a seamless manner. This enhances Reliability, Availability, and Serviceability of the system. The installing/relocating process is outlined belows:

1. Save and turn off the machine check enable bit for the processor doing the

instruction modification.

2. Store and synchronize a "b $" (branch-to-itself) instruction at...