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Method and Structure for Optimizing the Read Valid Data Window in an Addessable Memory Device Using Output Driver Impedance Adjustment

IP.com Disclosure Number: IPCOM000016092D
Original Publication Date: 2002-Jul-23
Included in the Prior Art Database: 2003-Jun-21
Document File: 5 page(s) / 230K

Publishing Venue

IBM

Abstract

Disclosed is an algorithm and associated implementation circuitry, for optimizing the read valid data window in an addressable memory device using output driver impedance adjustment. The below figure shows a general case of data bits (DQ (early) and DQ (late)) and strobe (DQS) received from a Double-Data-Rate (DDR) DRAM device. Only two data bits are shown, but the example is valid for any number of data bits greater than 1, which must be latched with the rising and falling edge of a single strobe. The data eye is the width, measured in time, in which all the DQ bits are valid. The strobe must rise once within a data eye, and fall within the next data eye. If the strobe rises or falls outside the data eye (in a region when one or more of the DQ bits is switching) then invalid data will be latched. The figure shows three types of error contributors related to the data. The Rise-Fall propagation error (RF prop error) is the distance between the start of the rising and falling edge for a particular DQ bit at the input to the memory control receiver. The skew between bits is the distance between the arrival times of the rising (or falling) edges of any two DQ bits clocked by the same strobe. The transition time error is the distance at the crossing point between the rising and falling edges in the transition region, minus the RF prop error. The crossing point, shown in the figure as a dotted line, is the reference voltage. The figure shows one type of error relative to the strobe: the strobe centering error. In the system shown, there are two primary objectives. The first is to maximize the size of the data eye. The second is to center the strobe's rising and falling edges within the data eye. In the following figure, the data eye is reduced by RF prop error, skew between bits, and transition time error. In spite of this, the strobe's rising edge is fairly well centered in the data eye. But this comes at the expense of centering the falling edge in the next data eye. The margin for the falling strobe edge is smaller than the margin for the rising strobe edge.

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  Method and Structure for Optimizing the Read Valid Data Window in an Addessable Memory Device Using Output Driver Impedance Adjustment

  Disclosed is an algorithm and associated implementation circuitry, for optimizing the read valid data window in an addressable memory device using output driver impedance adjustment.

The below figure shows a general case of data bits (DQ (early) and DQ (late)) and strobe (DQS) received from a Double-Data-Rate (DDR) DRAM device. Only two data bits are shown, but the example is valid for any number of data bits greater than 1, which must be latched with the rising and falling edge of a single strobe. The data eye is the width, measured in time, in which all the DQ bits are valid. The strobe must rise once within a data eye, and fall within the next data eye. If the strobe rises or falls outside the data eye (in a region when one or more of the DQ bits is switching) then invalid data will be latched.

The figure shows three types of error contributors related to the data. The Rise-Fall propagation error (RF prop error) is the distance between the start of the rising and falling edge for a particular DQ bit at the input to the memory control receiver. The skew between bits is the distance between the arrival times of the rising (or falling) edges of any two DQ bits clocked by the same strobe. The transition time error is the distance at the crossing point between the rising and falling edges in the transition region, minus the RF prop error. The crossing point, shown in the figure as a dotted line, is the reference voltage.

The figure shows one type of error relative to the strobe: the strobe centering error. In the system shown, there are two primary objectives. The first is to maximize the size of the data eye. The second is to center the strobe's rising and falling edges within the data eye. In the following figure, the data eye is reduced by RF prop error, skew between bits, and transition time error. In spite of this, the strobe's rising edge is fairly well centered in the data eye. But this comes at the expense of centering the falling edge in the next data eye. The margin for the falling strobe edge is smaller than the margin for the rising strobe edge.

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Figure 1: Memory Read Data Margin Detractors

We describe below an algorithm and related circuitry to reduce the RF prop error, the skew between bits, and the transition time error for the DQ bits, and to center the data strobe within the data eyes, thus minimizing all these sources of error.

JEDEC standard DDR DRAM-2 devices are proposed to vary their drive strength independently for low-to-high and high-to-low transitions, by varying the impedance, or drive strength, of off-chip driver (OCD) pull-up (PU) and pull-down (PD) devices. Besides altering the v...