Browse Prior Art Database

Synchronous start/stop in a multi nodal system

IP.com Disclosure Number: IPCOM000016108D
Original Publication Date: 2002-Jul-12
Included in the Prior Art Database: 2003-Jun-21
Document File: 7 page(s) / 90K

Publishing Venue

IBM

Abstract

1 Synchronous start/stop in a multi nodal system

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Synchronous start/stop in a multi nodal system

1 Synchronous start/stop in a multi nodal system
1.1 Scope This application describes a method to start all chips in a multi node system synchronously while the different chips are connected to different clock chips and each clock chip to a different cage controller.

Clock lines to chips

Clock lines to chips

Clock lines to chips

Clock lines to chips

...

...

...

...

Clock Chip

# 0

Clock Chip

# 1

Clock Chip

# 2

Clock Chip

# 3

Cage Cntl

# 0

Cage Cntl

# 1

Cage Cntl

# 2

Cage Cntl

# 3

Service Element

The service element (SE) gives the start command to all cage controllers. These cage controllers propagate the start command to the individual clock chips and the clock chips start the clocks to the connected chips. Each cage controller may add some unpredictable delay in the path from the SE to the clock chip. Thus the clock chips receive their individual start commands asynchronously in a random order.

1.2 Synchronization hardware

1

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To overcome these asynchronous start pulses from the cage controllers the clock chips synchronize each other. In a 4 node system each clock chip sends 3 copies of the local start signal to each of the other clock chips and receives 1 line from each clock chip.

When the clock chip receives a start command it raises the start/stop line to all other clock chips immediately and delays it by one cycle locally. The clock lines to the user chips get active if all external start/stop inputs are active and the locally delayed signal is active as well. There is an override bit locally on each clock chip that enables the clocks to the user chips regardless of the state of the input line. Thus the logic tolerates missing chips.

The stop sequence is exactly the same as the start sequence. The clock chip that detects a stop condition immediately drops the start/stop line to the other clock chips and delays the internal stop condition by one cycle. Thus all chip drop their clock lines to the user chips in the same cycle.

Star Structure

C lock C hip #0

C lock C hip #1

C lock C hip #3

C lock C hip #2

Star structure for connection between clock chips

2

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fr o m : to :

Wiring example for 4 clock chips

1.3 Limitations While above scheme perfectly fits the needs when the number of nodes is small (up to
4), it lacks scalability. As each clock chip talks to every other clock chip the number of connections between the clock chips increase with the number of nodes, and due to node packaging constraints the maximum delay (wire length) between the nodes also increases with the number of nodes.

1.4 Enhancements

fr 1

0

0

to 1

fr 2

1

to 2

1

fr 3

to 3

2

2

Clock Chip #0

fr 0

to 0 to 2 to 3

0

0

fr 2 fr 3

1

Clock Chip #1

1

2

2

fr 0

to 0 to 1 to 3

0

0

1

Clock C h ip #2

1

2

2

fr 1 fr 3

fr 0

to 0 to 1 to 2

0

fr 1 fr 2

1

0

Clock C h ip #3

1

2

2

3

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The limit...