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Browse Prior Art Database

Processor supporting asymmetric multithreading capability

IP.com Disclosure Number: IPCOM000016150D
Original Publication Date: 2002-Aug-11
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

Described is a microprocessor with multithreading capabilities. Typical multithreading designs require to replicate the entire processor state for all supported hardware threads, including, but not limited to, integer, floating point, condition registers segment registers TLBs counters, hardware triggers, timers special purpose registers According to the present invention, a microprocessor with multithreading capabilities is designed to have at least one thread which does not replicate the entire processor state for said thread, limiting the capabilities of this thread. This allows to reduce the design cost of adding additional threads by reducing the number of resources which need to be provided, multiplexers to select between several per-thread copies of resources, etc.

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Processor supporting asymmetric multithreading capability

Described is a microprocessor with multithreading capabilities. Typical multithreading designs require to replicate the entire processor state for all supported hardware threads, including, but not limited to,

integer, floating point, condition registers segment registers
TLBs counters, hardware triggers, timers special purpose registers

According to the present invention, a microprocessor with multithreading capabilities is designed to have at least one thread which does not replicate the entire processor state for said thread, limiting the capabilities of this thread. This allows to reduce the design cost of adding additional threads by reducing the number of resources which need to be provided, multiplexers to select between several per-thread copies of resources, etc.

Possible thread design choices include:

threads without floating point support: when a thread is issued to this unit, floating point support is disabled and all floating point operations are set to trap to the operating system. When a floating operation occurs, control passes to the operating system which will re-issue this thread to a floating point capable thread. This allows to provide additional threads without the cost of supporting the full floating-point state for use in integer-bound program. threads without memory address translation and/or memory protection: threads without memory protection can be used for low-level system mana...