Browse Prior Art Database

A Fast, Low Power Current Comparator in CMOS with Completion Logic

IP.com Disclosure Number: IPCOM000016167D
Original Publication Date: 2002-Aug-16
Included in the Prior Art Database: 2003-Jun-21
Document File: 6 page(s) / 76K

Publishing Venue

IBM

Abstract

A novel current comparator circuit, made in CMOS technology, for a fast and energy-efficient comparison of small currents. It is difficult to compare very small currents (less than 3·A difference) in a dynamic (i.e., clocked) system, working at high frequency (up to 400 Mhz). These include the following: 1. Speed (400 Mhz and higher)

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 6

A Fast, Low Power Current Comparator in CMOS with Completion Logic

A novel current comparator circuit, made in CMOS technology, for a fast and energy-efficient comparison of small currents.

    It is difficult to compare very small currents (less than 3·A difference) in a dynamic (i.e., clocked) system, working at high frequency (up to 400 Mhz).

These include the following:
1. Speed (400 Mhz and higher)
2. High resolution (< 2.2·A)
3. Low power (230 ·W at 50 Mhz)
4. Almost no kickback to the inputs, significantly reducing clocking noise
5. A completion signal that can be used for various applications, such as asynchronously timed systems

    The comparator works in two phases (see Figure 1 below).In the precharge phase, the comparator resets-both outputs go to Vmid, and the previous evaluation is erased. During this phase, positive feedback is canceled. At the end of the precharge phase, the clock goes high and the evaluation phase begins, in which the difference between the input currents is mirrored in the positive feedback loop (TP1, TP3, TN2, TN4). This loop amplifies the difference and eventually locks the proper digital value (that reflects the current difference of inputs) in the output nodes (vout, vout_n). A unique property of this circuit is that the feedback is not completely cancelled during the precharge phase. Instead, the upper (PMOS) part of the feedback loop (TP1, TP3) is kept in the triode region (rather than saturation), which saves power during the precharge phase, and enables faster switching in the evaluation phase. Changing the state of a MOS in the triode region to either cutoff or saturation is much faster than making the extreme move from saturation to cutoff. It should be noted that due to the symmetric structure of the circuit, one transistor (from the TP1, TP3 pair) is always in the cutoff regionduring evaluation. During the precharge phase, the completion signal is preset to logic "0" because the Vmid voltage is greater than the threshold voltage (Vt) of transistors TN2, TN4, thus the inputs to the OR gate are both logical "0". During the evaluation phase, once a decision is made, one output goes to "1" and the other to "0" (as a result of the positive feedback loop). Thus, the OR output goes to "1" and acknowledges that the evaluation has been completed.

    Figure 1 shows a typical oper...