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A Method to Enhance Reliability of Integrated Circuits By Introducing Electromagnetic Radiation At Pre-Fuse Test to Facilitate Defect Discover So That Redundancy May Be Invoked

IP.com Disclosure Number: IPCOM000016179D
Original Publication Date: 2002-Oct-18
Included in the Prior Art Database: 2003-Jun-21
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Abstract

Defects occurring in the silicon level of integrated circuits are difficult to detect during test , especially those that are not electrically active at the time of test (potential reliability fails). One method of enhanced defect detection is to use a high test temperature to aid in defect-induced leakage currents. This invention would use this elevated temperature test technique but introduce in addition to the temperature, electromagnetic radiation to enable a defect lying at or below the silicon surface to become electrically active and, thus become easily detectable. Once detected, redundancy may be invoked to replace the defective element with a non-defective one. One potential application which may be useful to the reduction of one memory related failure mechanism known as the "Variable Retention Time" or VRT fail follows. It should be noted that this invention not only pertains to this mechanism/technique, but may be applied to other defects/techniques as well (light, radio waves, etc.).

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  A Method to Enhance Reliability of Integrated Circuits By Introducing Electromagnetic Radiation At Pre-Fuse Test to Facilitate Defect Discover So That Redundancy May Be Invoked

  Defects occurring in the silicon level of integrated circuits are difficult to detect during test , especially those that are not electrically active at the time of test (potential reliability fails). One method of enhanced defect detection is to use a high test temperature to aid in defect-induced leakage currents. This invention would use this elevated temperature test technique but introduce in addition to the temperature, electromagnetic radiation to enable a defect lying at or below the silicon surface to become electrically active and, thus become easily detectable. Once detected, redundancy may be invoked to replace the defective element with a non-defective one. One potential application which may be useful to the reduction of one memory related failure mechanism known as the "Variable Retention Time" or VRT fail follows. It should be noted that this invention not only pertains to this mechanism/technique, but may be applied to other defects/techniques as well (light, radio waves, etc.).

The root cause of VRT fails are Silicon defects such as stacking faults and dislocations that, for various reasons become electrically active as a function of time (non time zero detectable). In all integrated circuits, ion implants or diffusions of other than host species are used to locally change conductive properties of the host Silicon or Ge lattice. This induces localized stresses and strains in the host lattice and, as a means to relieve th...