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C4-Fan-out Structure for High Density Packaging Disclosure Number: IPCOM000016184D
Original Publication Date: 2002-Aug-17
Included in the Prior Art Database: 2003-Jun-21
Document File: 5 page(s) / 80K

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Disclosed is a design for a structure to enable C4 fanned out structures for high density packaging.

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C4-Fan-out Structure for High Density Packaging

Disclosed is a design for a structure to enable C4 fanned out structures for high density packaging.


Flip-chip bonding with C4 (Controlled Collapse Chip Connection) has many advantages relative to conventional wire bonding packaging. C4 structure is a lead/tin ball over a transition metallurgy pad used in a flip chip package for providing interconnect between chip circuities to the outside world. Since the C4 bonding structure is short and wide, the impedance is significantly reduced, di/dt noise is minimized due to lack of inductive coupling. Therefore, C4 is ideal for packing of high-performance chips. Besides, C4 occupies the whole chip are which allow more I/Os than any other package. The bigger the chip size the more area and thus more I/Os can be provided. However, due to material and reliability constrains, C4 scales in a much slower rate than the integrated semiconductor devices. As the technology continues to scale, very soon that chip size will be dominated by the size of C4 and instead of circuits. For example, in a 0.10 um technology, the tightest C4 packing density is "4 on 9", that is, a 4 mil solder ball on 9 mil pitch, where 1 mil = 25.4um. The pitch of C4 balls is in the range of 225um to 230um. Therefore, in the next generation we will not able to provide sufficient I/Os by using C4 technology.

Background Flip chips or C4 has much higher packinging efficiency than wire bonding and TAB (upto 90%) and remains the top choice for 1st level packinging technology in high end electronic module. An earlier national technology roadmap report from Semiconductor Industry Association estimated the C4 bump counts will reach to 3000 on a single die of about 17 mm edge size, and the corresponding c4 bump pitch will be 130 microns for
0.13 micron technolgy [1]. US5297333 shows a typical method for making C4 interconnect for semiconductor device. In US5724729, in addition to C4 interconnects, it also shows a mechanism to cool a flip chip using a plurality of customized thermally conductive materials. Further redistribution of the electrical signal is done either by thick film and or combination of thin film/thick film wiring in the module [3,13]. An alternative approach is taught by US 6081026 where a interposer for providing power, ground and signal connections between the metal bumps (solder, paste, Au/Sn, Cu/Sn) on the dice and the 2nd level packaging. Yet another variation of high density integrated circuit packaging is achieved with chip stacking and via inteconnection as explained in US 6187678B1. For large bumps and relax pitches, C4 bumps on a chip can be fabricated by by silk screening of solder paste. For features of tighter ground rules (e.g. 10 mil diammter on 15 mil spacing or smaller), the C4 bumps are made by evaporation and electroplating [5]. However, volume uniformity control for thousands of solder bumps rapidly become a limiting factor in production...