Browse Prior Art Database

Original Publication Date: 2002-Nov-29
Included in the Prior Art Database: 2003-Jun-21
Document File: 4 page(s) / 93K

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The invention permits the construction of very high speed (GHz), low power CMOS ADC, with improved metastability behavior due to the use of the arbiter circuit, reduced clock power dissipation, and easier clock routing due to the use of self-timed circuits.

    The treatment of metastability errors by using an arbiter type circuit instead of relying on metastable hardened latches is new. The comparators that form the flash converter are built to provide a completion pulse indicating that a decision has been achieved.

    A ratioed wide OR circuit generates a pulse that indicates that most of the neighbor comparators have reached a decision (majority signal). The arbiter passes the logic value of the comparator if it arrives in time (before the majority signal), and passes a zero if the comparator has not reached decision by the time the majority signal arrives.

    The use of self-timed logic circuits in an ADC is new. There is no claim on the self-timed logic, but only on it's use in an ADC.

Description of Figures

Figure 1: Principle of Metastability Correction by Arbiter

    Figure1 describes the concept of using an arbiter to improve the metastability behavior of the ADC. The majority circuit in this example has three inputs. In practice, a larger number of inputs can be used (eight in our design).


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Figure 2: Waveforms for Arbiter Circuit

    Figure 2gives the simulated waveforms for the comparators and arbiter, as described in Figure1. In the first cycle, the comparator has a clean decision on zero, and in the second cycle, the comparator is metastable (actually, we get a late one).

Figure 3: Schematic of Arbiter Circuit


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Figure 3presents a possible implementation of the arbiter circuit.

Figure 4: Proposed Flash ADC Architecture

    Figure 4presents the block schematic of the proposed ADC architecture, with emphasis on the way the self-timed circui...