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Optimized structure for cooling of integrated circuit chips

IP.com Disclosure Number: IPCOM000016346D
Original Publication Date: 2002-Nov-24
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Abstract

Structure for Improved Cooling of Integrated Circuit Chips

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Optimized structure for cooling of integrated circuit chips

Structure for Improved Cooling of Integrated Circuit Chips

Disclosed is a structure where a material with a higher thermal conductivity than silicon is bonded into a cavity in the backside of an integrated circuit chip to reduce the peak temperature on the front surface of the chip, which contains the operating devices. The operating frequency of high performance chips is often limited by the maximum allowable junction temperature. Even with the use of state of the art chip design and packaging technology, the continuing miniaturization of the transistors and increase in operating frequency results in increased power density and greater difficulty in providing adequate cooling. Current cooling technologies have focused on reducing the thermal resistance of the path from where the heat is generated to the heat sink so as to minimize the temperature differential between the two. The maximum operating frequency of the chip is of course determined by the hottest area on the chip, where the temperature must be kept low enough to avoid premature failure of the device. 0Temperature gradients across the front of the chip can be as large as 10C to 150C in some cases. For example, where the system clock is generated often results in a local hot spot on the chip surface during operation.

By using the disclosed structure, where a material with a higher thermal conductivity than Si is bonded into a cavity formed from the back side of the Si substrate under the hot spot, the peak temperature on the chip surface can be reduced. This reduction is due to a reduced thermal gradient through the chip substrate and improved thermal spreading in the substrate. This reduction of the peak temperature enables the operating frequency of the chip to be increased while maintaining a low enough junction temperature to ensure adequate reliability.

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