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A Voltage Control Method of Graphics Controller using CPU power state

IP.com Disclosure Number: IPCOM000016359D
Original Publication Date: 2002-Oct-04
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Abstract

Disclosed is a voltage control method of graphics controller using CPU power state.

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A Voltage Control Method of Graphics Controller using CPU power state

Disclosed is a voltage control method of graphics controller using CPU power state.

CPU and graphics controller have power management function as below, but they work independently.

      Graphics controller monitors it's activities. When idle is detected, graphics controller drops the clock and voltage. CPU is controlled by chipset. The chipset monitors system activities. When chipset detects idle, then chipset enters CPU to low power state. In the current design, AGP bus is idle when CPU is low power state. In the view point of graphics controller, there is no data transfer in/to graphics controller when AGP bus is idle, so graphics controller is completely idle. Therefore graphics controller can stops clock frequency and drop the voltage.

Fig.1 shows the block diagram of New Method. VDDC is power line of graphics controller, and is generated by DC-DC for graphics controller. Graphics controller is connected with North Bridge by AGP bus. South Bridge controls CPU power management and AGP bus state. "-C3_STAT" indicates AGP bus idle state. In new method, DC-DC monitors "-C3_STAT". DC-DC controls VDDC as following table.

Fig.1 Block Diagram of New Method

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As above, VDDC is low level when graphics controller is completely idle.

Fig. 2 shows the function confirmation logic. In this logic, VDDC high level is 1.51V, middle level is 1.26...