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System write protection against microcontroller out of control

IP.com Disclosure Number: IPCOM000016416D
Original Publication Date: 2002-Dec-19
Included in the Prior Art Database: 2003-Jun-21
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Abstract

A system write protection against microcontroller or microprocessor out of control

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System write protection against microcontroller out of control

I. Problem Description

The problem to fix is, in a networking sytem based upon a microprocessor ,when this microprocessor become out of control , the configuration of the system must not be altered by some erratic microprocessor write access .

II. Applications of the Invention

Any machine or system wanting to protect vital system writable areas.

III.Description of the Invention

As described on figure 1, the heart of the invention is a state machine (SM) and a classical watchdog. This watchdog is reset by the micro controller when it is still under control. When the micro controller is disturbed by an electrostatic discharge (ESD) or any fetch problem, it becomes out of control, and can change the configuration of the switching parameters, so we need to prevent this behaviour.

data bus (8 bits)

OSM

M icrocontroller

data

/W R regs

SW ITCH

data

/CS

/W R

R

/W R enable

/W D elapsed

WD

/R eset

Figure 1

  The switch device is programmed via the 'data' bus and it's '/write regs' commands. If the '/write regs' lead remains inactive, the internals regs will not be altered. So, we will act on this lead to enable or disable this function.

  The 'watchdog' is a stand alone running machine needing a periodic 'reset' in order to have an inactive '/wd elapsed' output lead. When the micro controller is no more able to reset this watchdog via the chip select :'cs' output, the '/wd elapsed' become active and feeds the state machine block:'sm'.

As described on figure 2, the state machine waits for a 'wd elapsed' event in sate 0.

When th...