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Method for self-testing high-speed I/O buffers not connected to a tester

IP.com Disclosure Number: IPCOM000016501D
Publication Date: 2003-Jun-25
Document File: 2 page(s) / 130K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for self-testing high-speed input/output (I/O) buffers not connected to a tester. Benefits include an improved test environment, improved test performance, and improved reliability.

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Method for self-testing high-speed I/O buffers not connected to a tester

Disclosed is a method for self-testing high-speed input/output (I/O) buffers not connected to a tester. Benefits include an improved test environment, improved test performance, and improved reliability.

Background

� � � � � During high volume manufacturing (HVM) all I/O buffers are tested for timing marginality by tester. A low speed, low pin count tester is used conventionally for cost savings. For example, a chip with ~550 pins and a double data rate (DDR) bus that runs up to 400 MHz is being tested by a 155-MHz 256-channel tester. With two pins sharing one tester channel, the pin limitation remains an issue.

� � � � � Functional testing requires all pins to be connected with tester channels, but structural testing does not require it. Structural testing alone cannot provide the required fault grade for the chip. As a result, functional testing is required.

� � � � � The pin limitation problem is unique to high pin-count chips. Previous generation chipsets did not have the pin limitation issue. The pin count was low, and two pin tester channel sharing was adequate. In some cases, relays were used to assign more than two pins to one tester channel for structural testing only. Due to the speed increase of the I/O buffers, the relay solution is no longer practical because relays add extra loading and cause electrical issues.

        � � � � � Conventionally, the chip drives output pins and the tester strobes them to check the functionality of the chip.

Description

        � � � � � The disclosed method is the self-testing of high-speed I/O buffers not connected to a tester. Purely output-type pins are grouped together without being assigned to any tester channels. The pins are looped back from the I/O pad. Their state is stored in a multiple input signature register (MISR) when valid data are driven o...