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CMOS Ratio-insensitive LSSD compatible latch

IP.com Disclosure Number: IPCOM000016545D
Original Publication Date: 2003-Jun-27
Included in the Prior Art Database: 2003-Jun-27
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Abstract

A CMOS LSSD latch which is insensitive to device ratios and functions well at low voltage.

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CMOS Ratio-insensitive LSSD compatible latch

    Yuan and Svensson(1) describe two, single write port, ratio-insensitive latches. One requiring a positive active clock, and the other requiring a negative active clock. The ratio-insensitive property is desirable for functionality at low voltages. However, these latches are not LSSD compatible. We have merged their two latch designs into one, with a separate write port for a scan input and a data input, making it LSSD compatible, while maintaining the ratio-insensitive property. Further, when used in an application such as a register array with bit write control, it is possible to eliminate one transistor making the latch physically smaller.

Figure lvcell.tiff shows the latch schematic.

Figure bw.tiff shows a bit write control circuit which might be used to drive the data port in an application such as a register array.

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Other ratio-insensitive LSSD compatible designs use transmission gates. These require both a clock and it's compliment for each write port which make it difficult to physically wire. This design requires only one clock polarity per write port.

(1) Jiren Yuan and Christer Svensson, "New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings", IEEE Journal of Solid-State Circuits, Vol 32, No. 1, Jan 1997.

Disclosed by International Business Machines Corporation

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