Browse Prior Art Database

Enhanced Flash Memory Reporting Mechanism

IP.com Disclosure Number: IPCOM000016626D
Original Publication Date: 2003-Jul-07
Included in the Prior Art Database: 2003-Jul-07
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Abstract

Today Flash memory technology is becoming more dense. Some servers even store the entire operating system and diagnostics on a series of Flash modules. In the past Flash modules held data that was more or less immune to data integrity problems. With the denser flash memories and with the smaller cell sizes, the incidence of single bit errors increases. This increase is then multiplied by the number of Flash modules in a system. When the system boots and there is a single bit error, the system must keep running by applying an Error Correcting Code (ECC) to the data. However, I/O pins are limited on the module and there is a requirement to ensure the same footprint is used for different size families of Flash modules e.g., 32 Megabit, 64 Megabit, 128 Megabit etc. It is not practical to use an I/O pin as an indication of an ECC error. The following circuit and command sequence allow the user to interrogate internal registers to determine if an ECC error occurred, the address or addresses that had the ECC error, and the number of ECC errors during this operating system load.

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Enhanced Flash Memory Reporting Mechanism

      Unlike Synchronous Dynamic Random Access Memories (SDRAM) a flash failure is permanent and cannot be "cleaned" by a write operation. So it is imperative to know how many single bit failures have occurred during software loads. This knowledge leads to a predictive failure analysis so preventative maintenance can be performed. The following diagram shows the additional circuitry (shown in red) required to allow a program to interrogate flash failures, record them and if necessary perform preventative maintenance.

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ECC Verify

Enab

EC


ECC Counter

Address FIFO

Error Register

    A modification of the finite state machine (FSM) is needed to allow it to accept an ECC error indication from the ECC logic. When an ECC error is detected, the FSM sets a bit in the error register indicating an error occurred, increments the ECC counter, and loads the address of the data that is corrupted in an address queue. Each time an error occurs, the ECC counter is incremented and the offending address stored in the FIFO queue. This information is held in these registers until interrogated by the system. When this information is accessed, it is immediately cleared and waits for the next flash

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access.

    The key to obtaining the data is to use a similar command sequence used today in flashing modules. This command sequence "opens" a window and allows the flash module to respond with the correct information. First, a series of writes to specific addresses with specific data enables the reading of the ECC registers. Once this read window...