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Method for a noise rejection circuit that incorporates logic blanking and timed hysteresis control to eliminate false triggering due to noisy input signals

IP.com Disclosure Number: IPCOM000016694D
Publication Date: 2003-Jul-09
Document File: 5 page(s) / 86K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a noise rejection circuit that incorporates logic blanking and timed hysteresis control to eliminate false triggering due to noisy input signals. Benefits include improved performance.

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Method for a noise rejection circuit that incorporates logic blanking and timed hysteresis control to eliminate false triggering due to noisy input signals

Disclosed is a method for a noise rejection circuit that incorporates logic blanking and timed hysteresis control to eliminate false triggering due to noisy input signals. Benefits include improved performance.

Background

        � � � � � Noise on input pins of microprocessors plays a crucial role in conventional designs. Their� increased complexity leads to an increased density of signals. With increased signal speeds, increased switching and cross-talk noise are produced. The continued reduction of supply voltages reduces noise-margins and results in a general degradation of overall system noise immunity. Cost pressures that contribute to a reduction in the number of layers and an increased variability of line parameters produces an overall reduction in signal quality. In many designs, signals that are more critical in terms of noise and speed get the shortest routes while signals that are slower and somewhat less timing critical end up with longer routes. These noncritical designs and signals produce the worst noise levels and signal integrity. Backwards design compatibility to legacy systems forces even newer designs to stick to design requirements that are conventionally deemed marginal.

        � � � � � These noise factors force silicon designers to continually improve their receiver noise immunity on newer designs, presenting a challenge as reduced supply voltages continually degrade the noise rejection of input receivers. One example is the design of a noise rejecting input receiver where the incoming signal is expected to be nonmonotonic in the voltage band around the switching region of the input receiver. If the nonmonotonic behavior is caused by noise that is above (or close to) the frequency bandwidth of the input receiver, the problem is easier to resolve. However, if the noise frequency falls within the bandwidth of the receiver, the solution increases in complexity depending on the frequency and the magnitude of the noise spectrum.

        � � � � � Several conventional solutions address these concerns. The use of noise filters to filter out noise that lies within the bandwidth of the receiver is one technique. For example, a filter can block out input noise (see Figure 1). Filters can be low-pass, high-pass or band-pass. A low-pass filter rejects frequencies higher than its cut-off frequency. A high-pass rejects frequencies lower than its cut-off. A band-pass permits only frequencies within a certain band of frequencies to pass. Depending on the nature of the noise, one or more filters can be utilized.

        � � � � � Hysteresis can also be used to block noise. For example, a sense-amplifier is used at the input (see Figure 2). Hysteresis is achieved through the use of an output-controlled reference generator. The reference voltage is shifted in a direction opposite to the input signal. In this examp...