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Method for a low latency tag pipeline for a high-level cache

IP.com Disclosure Number: IPCOM000016699D
Publication Date: 2003-Jul-09
Document File: 2 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a low latency tag pipeline for a high-level cache. Benefits include improved performance.

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Method for a low latency tag pipeline for a high-level cache

Disclosed is a method for a low latency tag pipeline for a high-level cache. Benefits include improved performance.

Background

              A high-level cache (level-3 and above) typically has a large capacity but low utilization because the request is fulfilled by the lower level caches a majority of the time. Tag lookup requires multiple cycles. Data access requires a greater number of cycles. The look-up time must account for sending request information to a large area and getting back the results. As a result, many tag lookups involve at least 1 cycle for resistance-capacitance (RC) delays. Data lookups involve multiple cycles for RC delays.

              Conventional design theory includes the concept that the latency observed by all the accesses should be uniform.

General description

              The disclosed method is a cache design that reduces the overall latency of the tag pipeline of a high-level cache. The cache is organized in two or more sections to provide early response for a subset of the requests, resulting in an overall improved access latency.

              The key elements of the disclosed method include:

•             Tag pipeline with overall lower latency

•             Tag array divided across ways

•             Tag array divided across sets

Advantages

              The disclosed method provides advantages, including:

•             Improved performance due to improved response (reduced latency) to a subset of requests because the cache is organized in two or more sections

•             Improved performance due to preventing unnecessary replication of tag comparator and error checking and correction (ECC) hardware when the tag array is divided across ways

·        Improved performance due to potential concurrent access of the two halves when the tag array is divided across sets

Detailed description

              The disclosed method includes atag pipeline with overall lower latency. For example, the conventional tag lookup of a high level cache requires at least 1 cycle to reach all the elements of the tag array. This delay introduces an additional cycle to the latency of the high-level cache. The individual elements of the cache can be reorganized into two sections, a section that provides tag look-up results early and a section that takes additional cycle(s) to complete the lookup. The results of the tag lookup arrive early or late, depending on which section provides the fina...