Browse Prior Art Database

Generic Partitioning of the Floating Point Space for the Verification of Microprocessors

IP.com Disclosure Number: IPCOM000016799D
Original Publication Date: 2003-Jul-16
Included in the Prior Art Database: 2003-Jul-16
Document File: 4 page(s) / 53K

Publishing Venue

IBM

Abstract

This invention generally relates to the functional verification of microprocessors, and more specifically relates to an apparatus and a method preferable for testing Floating point (FP) operations for compliance with their architectural specification.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 35% of the total text.

Page 1 of 4

  Generic Partitioning of the Floating Point Space for the Verification of Microprocessors

Invention

This invention generally relates to the functional verification of microprocessors, and more specifically relates to an apparatus and a method preferable for testing Floating point (FP) operations for compliance with their architectural specification.

Problem

    Floating point (FP) operations, which play a major part in modern processors, are used to support arithmetic and graphical capabilities. The functional verification of those operations is very challenging due to the huge data space. An operation on some data, which causes a result that does not match the expected result according to the architectural specification, is a bug. Such a bug in a processor sent to the market may cause an enormous expense. For example, the Pentium* FDIV bug (see reference number 3) cost Intel around $500 million.

    While the space of a single FP operand may contain 2^80 elements (for an 80 bits FP number), the amount of values which is feasible to check is just a few dozen billions (less than 2^40), given the current standard verification resources, and time-to-market requirements. Hence, it is a given fact that only a negligible part of the space of the FP values might be exercised during the whole verification process. This stresses the importance of the right selection of FP values, so that their verification confers a reasonable degree of confidence in the FP design correctness, even though they represent only a negligible subset of the whole space.

    A common approach for testing FP operations for wrong results includes setting the operands of the FP operation to some value, prior to the execution of the operation. Random and boundary values, such as zero, which are clear from the architecture definition, are being checked, in addition to special values, which are design dependent. But since short cuts are used during the FP calculations, it has become harder to define which values to choose. In order to extend those checks, it is desired to add generic special cases, which are not foreseeable by the architecture specification.

Figure 1 presents a template of a Floating Point number ( x {0,1} ).

Sign Exponent Mantissa

x

xxxxxxxxxxxxxxxxxxxxxx

Figure 1: Floating Point number

    FP operands consist of one or more FP numbers of the following: There are several types of FP numbers. Single and double FP formats are specified in the IEEE Standard for Binary Arithmetic (see reference number 5). Extended format is specified in the Pentium Processor Family Developer Manual (see reference number


6).

Solution

    In order to achieve adequate partitioning of the FP space, a generic layer is added, constructing the following FP space partitions:

1. Architecture
2. Design specific

xxxxxxxx

Page 2 of 4

    3. Inter-architecture Accumulated experience and FP bug analysis have shown that there are architecture-independent cases that are typically more bug-prone in a design. Altho...