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Method for a pad architecture to reduce the pin count sort

IP.com Disclosure Number: IPCOM000016806D
Publication Date: 2003-Jul-16
Document File: 4 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a pad architecture to reduce the pin count sort. Benefits include an improved test environment and improved throughput.

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Method for a pad architecture to reduce the pin count sort

Disclosed is a method for a pad architecture to reduce the pin count sort. Benefits include an improved test environment and improved throughput.

Background

              In the test environment, more items must be tested without increasing the number of input/output operations. Additionally, multiple nodes must be tested concurrently.

             

              When the number of I/O pins exceeds 600 pins, the pin count sort must be reduced.

              In conventional applications, one pad leads to one set of circuits, leading to a large number of I/O pads (see Figure 1). The layout pad is typically limited, making the sort difficult because of having to probe many pins.

Description

              The disclosed method is a pad architecture to reduce the pin count sort. One pad can be used as the input to several circuits. The pad’s polarity and voltage can be used to trigger as many as four circuits. This method can be used for high-density logic test applications. It is compatible with bump and wire bond technologies. The method is useful for testing flash, chip set, and logic sort.

              A more complex I/O test arrangement can be enabled (see Figure 2). Four circuits can be connected to one pad and one probe contact.

              The disclosed method uses features of the layout and the tester (see Figure 3). The tester acts like a current sensor and like a voltage source.

Advantages

              The disclosed method provides advan...