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Method for a stubless multidrop bus interconnect

IP.com Disclosure Number: IPCOM000016807D
Publication Date: 2003-Jul-16
Document File: 5 page(s) / 111K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a stubless multidrop bus interconnect. Benefits include improved performance.

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Method for a stubless multidrop bus interconnect

Disclosed is a method for a stubless multidrop bus interconnect. Benefits include improved performance.

Background

� � � � � A requirement has been identified for a high bandwidth, low loss front-side bus (FSB) interconnect in computing platforms. Stubs must be eliminated. The increasing layers and trace technology-related costs of motherboards conventionally used for bus routing must be eliminated.

� � � � � The conventional bus interconnect is comprised of the bus traces routed on the motherboard with spacing designed to minimize crosstalk (see Figure 1). When a component connects (hard-wires) into this bus, physical trace connections are made through the socket interconnect and the package substrate into the die input/output (I/O) circuits. The length of the physical interconnect, typically ~1 inch, is referred to as the stub length. Because stubs are designed to have the same impedance as the bus I/O traces on the motherboard, they introduce a significant impedance discontinuity at the junction of the component and the bus (see Figure 2). For example, the graphic illustrates three junctions, the Northbridge chip, and the two inner CPUs to the FSB. While the circuits may be tri-stated or placed in a high-impedance state, all the stubs appear as open-ended lengths of interconnect that degrade signal integrity very significantly through multiple reflections.

General description

� � � � � The disclosed method is a stubless multidrop bus interconnect. This interconnect architecture provides high density, high performance I/O routing in a system requiring the parallel hard-wired connection of a number of integrated circuit chips to a communications bus.

        � � � � � The key elements of the method include:

•        � � � � Multidrop bus interconnection scheme that eliminates the trace lengths from a bus into a very large scale integration (VLSI) chip through the direct attachment of a component segment of the bus to the VLSI die

•        � � � � Bus architecture that greatly enhances the data transfer rates or bus bandwidth in typical multidrop bus applications, such as the FSB of computing platforms and memory buses that span a large number of memory chips

•        � � � � High performance, contained, flying I/O bus interconnection that eliminates the complexity of motherboard high-speed routing through the placement of the routing into a 2- or 3-layer flexible interconnect medium

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Improved performance due to the elimination of stubs

•        � � � � Improved performance due to a contained, potentially very low-loss bus interconnect medium

•        � � � � Improved performance due to the elimination of socket and package substrate discontinuities in the bus pathways

Detailed description

        � � � � � The disclosed method provides a hard-wired connection to the circuits on a VLSI chip directly from a component segment of a bus that is attached t...