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Method for integrated circuit package power rail bussing

IP.com Disclosure Number: IPCOM000016811D
Publication Date: 2003-Jul-16
Document File: 4 page(s) / 130K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for integrated circuit package power rail bussing. Benefits include an improved test environment and improved performance.

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Method for integrated circuit package power rail bussing

Disclosed is a method for integrated circuit package power rail bussing. Benefits include an improved test environment and improved performance.

Background

Conventionally, solder bump technology (see Figure 1) connects the power grid between the unit under test (UUT) and the test tool. Typically, the power and ground connection are laid out linearly (see Figures 2 and 3). The conventional bump pattern alternates power and ground bumps (see Figure 4).

Description

        � � � � � The disclosed method utilizes solder rails instead of solder bumps for connecting the power grid between the unit under test (UUT) and the test tool (see Figures 5 and 6). This power bus approach enables the connection area of the power bus to be nearly doubled (see Figure 7). The method can be used for any die-to-package, package-to-interposer, or package-to-package power connection.

        � � � � � The primary advantage is that when creating power or core bussing, the amount of contact area can be nearly doubled, conserving surface area on the base of the die or interposer device (see Figure 8). This approach also results in lower loop inductance, resistance, and current-handling capabilities.

        � � � � � The doubling of the connection area enables either increased electrical performance or a reduction in cost through the reduction of required support structures while maintaining performance. The rail design is marginally faster to implement in design and i...