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Method for special uop handling in the macroinstruction flow

IP.com Disclosure Number: IPCOM000016821D
Publication Date: 2003-Jul-16
Document File: 2 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for special micro-operation (uop) handling in the macroinstruction flow. Benefits include improved performance.

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Method for special uop handling in the macroinstruction flow

Disclosed is a method for special micro-operation (uop) handling in the macroinstruction flow. Benefits include improved performance.

Background

        � � � � � Conventionally, when fetching instruction bytes, special uops may be required in between the fetches that do not correlate directly to the instruction bytes. Examples include the deallocation of entries from the victim cache array, uncacheable code fetches, and table lookaside buffer (TLB) misses. In former 32-bit architecture-based products, special uops flowed with the instruction bytes into the queue situated in front of the instruction rotator. This technique causes complexity and timing problems in the queue design because multiple uops could be pending in the queue without synchronization with the instruction bytes. The complexity increases as the number of entries in the queue increases. These special uop requests are typically rare, representing machine serialization.

Description

        � � � � � The disclosed method is special uop handling in the macroinstruction flow (see Figure 1). The queue handles only one special uop at the time. This technique is accomplished by detecting when a special uop request is pending. Instruction queue logic signals that the buffer is full until all instructions/special uops are processed. Only then are additional special uops allowed to enter the queue. This approach simplifies the logical complexity of handling uops and resolve...