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LSSD Scan Design Enhancement for Logic Diagnostics

IP.com Disclosure Number: IPCOM000017002D
Original Publication Date: 2003-Jul-22
Included in the Prior Art Database: 2003-Jul-22
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Abstract

Disclosed is a solution to the latch-adjacency problem that exists on current LSSD designs. The solution is to add a third latch so there is no dependency on previous latch states.

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LSSD Scan Design Enhancement for Logic Diagnostics

   Disclosed is a solution to the latch-adjacency problem that exists on current LSSD designs. Latch adjacency prohibits certain transition combinations from occurring on adjacent latches since the final state of a latch is dependent on the initial state of the previous latch.

     One solution to this problem is to do a parallel load. To do a parallel load, the L2 of each latch block is loaded via a normal scan. The L1's are then loaded by applying a system "c1" clock. This will load the L1 latches with the values from the system logic that feeds them.

     There are two main drawbacks to this solution. First, it may not be possible to load all the necessary L1 latches via the logic, especially if many L1 latches need to be set to a specific value. Secondly, it can take days or weeks to simulate the logic to determine what values are needed to perform a parallel load.

     The disclosed solution is implemented by adding a third latch (L3) to the latch block. This idea removes both of the drawbacks described earlier. Since any transition can be scanned into any latch (including adjacent latches), there is no need to perform a parallel load.

     The L3 latch will have a "c" clock and "c3" clock input. Both clocks will latch the value from the L2 latch into the L3 latch. The "c" clock is generated externally in test mode, and the "c3" clock is generated internally in system mode. Refer to Figure 1 - Latch Block Diagram.

Figure 1 - Latch...