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Concept for automatically selective clocking of synchronous circuitry Disclosure Number: IPCOM000017069D
Original Publication Date: 1999-Oct-01
Included in the Prior Art Database: 2003-Jul-22
Document File: 4 page(s) / 34K

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Thomas Ehben: AUTHOR


Today’s semicustom design flows require circuits to consist of large single-clocked state machines.

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Concept for automatically selective clocking of synchronous circuitry

Idee: Thomas Ehben, München

Today’s semicustom design flows require circuits to consist of large single-clocked statemachines.

Circuit concepts that derive internal clock signals from internal data can’t be handled by mostdesign compilers and are hard to test with modern test methodologies.

However, the downside of today’s design style is that clocking large amounts of flipflops at thesame clock speed regardless of whether they are told to receive new data via the the individual“write enable“ inputs leads to excessive void power consumption.

One way out of this dilemma is to switch complete clock domains within the circuit on or off bysoftware, i.e. by the user. This implies that the software development process gets involved in thehardware optimization process and thus makes the project work for a complete system muchmore difficult.

This concept shows a way to build state machines that can be handled by today’s design toolsand saves power at the same time without the need of software control.The basic principle is thatflipflop domains that don’t receive new data during a given clock cycle are cut off the clockduring that cycle thus reducing the wire load and the number of input loads to be toggled with theclock frequency. The starting point for applying this concept is a domain with registers having“write enable“ inputs that are connected together, i.e. either all or no registers of that domain aresupposed to take over their individual data in a given clock cycle.

Siemens Technik Report

Jahrgang 2  Nr. 5  Oktober 1999

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clock buffer

clock to domain

master clock

write enable

Figure 1: Poor man’s clock gating – Not recommended!

The easiest way would be to insert a gated clock driver into the domain’s clock net and have itcontrolled by the common “write enable“ signal. That gated clock signal could be connected toevery flipflop in the domain, now without “write enable“ inputs (fig. 1). Unfortunately, this doesn’twork well for two reasons: First, there are likely to occur glitches on the “write enable“ signalaround the active clock edge propagating through the gated buffer to the flipflops. Second, theclock signal is likely to arrive at the flipflop’s clock input one clock cycle too early due to scueand delays on the “master clock“ and the “write enable“ lines.

The solution to this problem is to delay the control of the gated clock buffer by half a clock cycleas shown in fig. 2 with the timing according to fig. 3.

The gated clock buffer is now controlled by an intermediate fl...