Browse Prior Art Database

I/O-Port for Digital Processors, addressable as a register

IP.com Disclosure Number: IPCOM000017138D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jul-22
Document File: 2 page(s) / 27K

Publishing Venue

Siemens

Related People

Dr. Xiaoning Nie: AUTHOR

Abstract

Conventional ports for external data input and output on a digital processor are accessible through a memory-mapped interface so that the I/O-port is addressed in the same way as memory. Such addressing is in most cases realized as indirect addressing, leading to the overhead of loading the I/O-port address into the base register first. One solution to avoid this overhead is to implement the addressing of the I/O-port as a register access. The timing of transfers between port and processor is the same as of usual register accesses, and the data transfer itself is bitwise addressable. An additional op-code for the port can be sent together with other data transfer information in one command, making it suitable especially for operations such as high-speed modem communications and bit manipulation.

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Bauelemente

I/O-Port for Digital Processors, addressable as a register

Idee: Dr. Xiaoning Nie, Vaterstetten

Conventional ports for external data input and output on a digital processor are accessiblethrough a memory-mapped interface so that the I/O-port is addressed in the same way asmemory. Such addressing is in most cases realized as indirect addressing, leading to theoverhead of loading the I/O-port address into the base register first.

One solution to avoid this overhead is to implement the addressing of the I/O-port as aregister access. The timing of transfers between port and processor is the same as of usualregister accesses, and the data transfer itself is bitwise addressable. An additional op-codefor the port can be sent together with other data transfer information in one command,making it suitable especially for operations such as high-speed modem communications andbit manipulation.

Unidirectional port interaction can be implemented as load/store instructions. Bidirectionalsupport can be established by making use of asynchronous interrupt mechanisms, which canin turn be coupled with the task switch mechanism of the processor - if available.

For example, a typical� � load� � instruction, which reads� � amount� � bits from� � port� � into the memoryaddress in� � base_register� � at position� � bit_position� , considering the application-specific op-code� � op� � and, if the� � wtback� � flag is set, shift to the next addressing register(� base_register� ++), c...