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Reducing skew between different clocks of a module during scan

IP.com Disclosure Number: IPCOM000017681D
Original Publication Date: 2001-Jul-01
Included in the Prior Art Database: 2003-Jul-23
Document File: 2 page(s) / 17K

Publishing Venue

Siemens

Related People

Balakrishnan Prashant: AUTHOR

Abstract

Clock Skew between multiple clock domains in a module: A SOC design has many hierarchical modules with each module having independent clocks. These days most chips have multiple clock domains and hence any module could have clock speeds from very fast to very slow clocks. In scan mode of operation typically the same clock would be used, which means that all these multiple clock domains would run at the same clock frequency. After the layout of the module, it would be noticed that the skew between these different clock domains in the scan mode is a lot. This means, that a lot of capture violations during scan mode of operation and hence a lot of instability of the test pattern would occur. The consequence would be a loss of fault coverage. Problems with Layout tool: When there are different clock input pins to a module, the layout tools are not able to take care of the relationship with different clocks. After layout, a clock tree synthesis is performed by the layout tool to balance the load on the clock nets and hence control the skew between different clocks. Hence the clock tree synthesis takes care of the individual clocks only and the skew between different clocks has to be controlled manually. A loss of some accuracy follows and there is no clean data flow during the scan mode of operation.

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Bauelemente

Reducing skew between different clocks of a module during scan

Idee: Balakrishnan Prashant, Singapore

Clock Skew between multiple clock domains in a module: A SOC design has many hierarchicalmodules with each module having independent clocks. These days most chips have multiple clockdomains and hence any module could have clock speeds from very fast to very slow clocks. Inscan mode of operation typically the same clock would be used, which means that all thesemultiple clock domains would run at the same clock frequency. After the layout of the module, itwould be noticed that the skew between these different clock domains in the scan mode is a lot.This means, that a lot of capture violations during scan mode of operation and hence a lot ofinstability of the test pattern would occur. The consequence would be a loss of fault coverage.

Problems with Layout tool: When there are different clock input pins to a module, the layout toolsare not able to take care of the relationship with different clocks. After layout, a clock treesynthesis is performed by the layout tool to balance the load on the clock nets and hence controlthe skew between different clocks. Hence the clock tree synthesis takes care of the individualclocks only and the skew between different clocks has to be controlled manually. A loss of someaccuracy follows and there is no clean data flow during the scan mode of operation.

Solution: To achieve 100% fault coverage of all chips, a full scan methodology is adopted. Layouttools will do a good job with the „Gated Clock“ within a module. A „Gated Clock“ can be anyclock which is logically controlled by a different selection, for example through a multiplexer. So,an additional clock pin for scan control is created which works in the scan mode of operation asthe scan clock for the whole module. In the normal mode, the multiple clock inputs are active.This concept is used to create a structure, which reduces the skew between different clock inputsto the module to a minimum. This is sh...