Browse Prior Art Database

High-to-low voltage level shifter without quiescent current using a low voltage CMOS (complementary metal-oxide semiconductor) process

IP.com Disclosure Number: IPCOM000017841D
Original Publication Date: 2001-Oct-01
Included in the Prior Art Database: 2003-Jul-23
Document File: 1 page(s) / 133K

Publishing Venue

Siemens

Related People

Sven Derksen: AUTHOR [+3]

Abstract

Enhancement in integrated circuit technology has led to a shrink in feature size of the active devices, which in company with the need for a reduction of power consumption led to a reduction of the supply voltage of integrated circuits (ICs). Widely accepted values for the supply voltage of modern ICs are 3.3V or 2.5V. On the other hand, many other components used by systems still operate on a higher supply vol- tage, i.e. 5V.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Energie

High-to-low voltage level shifterwithout quiescent current using alow voltage CMOS (complementarymetal-oxide semiconductor) process

Idee: Sven Derksen, Duisburg;

Dr. Michael Schmidt, Bottrop;Michael Zimmermann, Essen

Enhancement in integrated circuit technology has ledto a shrink in feature size of the active devices, whichin company with the need for a reduction of powerconsumption led to a reduction of the supply voltageof integrated circuits (ICs). Widely accepted valuesfor the  supply  voltage  of  modern  ICs  are  3.3V  or2.5V.  On  the  other  hand,  many  other componentsused by systems still operate on a higher supply vol-tage, i.e. 5V.

Up to now, the interface problem has been solved byusing process technology options, which make high-voltage  active  devices  available. By using thickergate oxide with these special devices a higher voltagecan be applied to their gates. The input section ofinput-output pad cells is constructed with these speci-al high-voltage transistors, shifting the high-voltageswing at the input to a low-voltage swing, which canbe applied to the core.

The  solution  presented  here uses a low-voltageNMOS (negative-channel  metal-oxide  semiconduc-tor)  transistor  (M1)  with  its  gate  connected  to theinternal supply voltage VDD, its source connected tothe pad input and its drain connected to the input of afollowing Schmitt trigger. An input voltage from 0Vup to approximately VDD minus the threshold volta-ge of the NMOS transistor (VTN) is tranfered un-changed to the input  of  the  Schmitt  trigger,  whileinput voltage above this threshold are blocked fromthe input of Schmitt trigger.

Node x, the input of the Schmitt trigger is held atVDD-VTN by this configuration. Thus, in all pos-sible conditions, the gate-sourc...