Browse Prior Art Database

Central Interrupt System for Dual-or Multi-Core Dies such as S-Gold or M-Gold

IP.com Disclosure Number: IPCOM000017954D
Original Publication Date: 2001-Oct-01
Included in the Prior Art Database: 2003-Jul-23
Document File: 2 page(s) / 155K

Publishing Venue

Siemens

Related People

Gerhard Forster: AUTHOR

Abstract

The technical problem refers to a central interrupt handling for all cores and co-processors (for S-Gold e.g. PCP2). Until now, for every core and every co- processor one interrupt unit was used. The new solu- tion consists of using one flexible interrupt unit in- stead of one interrupt unit for every single core / co- processor. The following description informs the reader about the functional and principal of the idea (as outlined in the figure below):

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Information / Kommunikation

The technical� problem� refers� to� a� central� interrupthandling for all cores and co-processors (for S-Golde.g. PCP2). Until now, for every core and every co-processor one interrupt unit was used. The new solu-tion consists of using one flexible interrupt unit in-stead of one interrupt unit for every single core / co-processor.

The following description informs the reader aboutthe functional and principal of the idea (as outlined inthe figure below):

1)� � � � One of the available Interrupt sources is fired.Any other and all further Interrupts go throughthe same process chain (steps 2 to 4). A periph-eral can have a set of Interrupt lines / sources, ofcourse.

•� � Each Interrupt source relates to a certain prioritylevel. Each Interrupt source has a unique ‘Inter-rupt code’.

2)� � � � A� raised� Interrupt� delivers� its specific prioritylevel over a multi-wire bus to a so-called ‘Prior-ity Decoder’; this� ‘Priority� Decoder’� translatesthe Interrupt source’s priority level into an ad-dress. After the destination address is calculated,a raised Strobe line can indicate that the ‘Inter-rupt code’ can be sent now from the peripheral’sInterrupt source.

•� � if we assume e.g. a total of 64 Interrupt sources,6 bit are enough to assign each Interrupt sourcean own ‘Interrupt code’.

3)� � � � The e.g. 6-bit ‘Interrupt code’ is now written intothe so-called Interrupt Buffer (for example over ahigh-speed 2-wire serial interface) at the previ-ously� calculated� destination� address. Addition-ally after writing this date to the Interrupt Buffer,the appropriate Valid Flag is set. Since the ‘In-terrupt code’ represents a unique identifier of anInterrupt source, after Interrupt handling is en-abled (for the first time or any further time) the‘Interrupt code’ can be interpreted by the on-chipHardware Interrupt� Control� instance,� the� so-called Interrupt Executor

•� � the width of the Interrupt Buffer depends on thenumber of available Interrupts, e.g. 64 Interruptsources require a� 6-bit� code,� 128� Interruptsources a 7-bit code, ... .

•� � the depth of the Interrupt Buffer is also related tothe max. number of Interrupt sources; it must atleast� be� as� deep� as� the max. Interrupt source

count.� For� 64� Interrupt� sources the InterruptBuffer must provide at least 64 storage locations,for 128 Interrupt sources at least 128 memory lo-cations must be provided, ... .

•� � Let’s assume� that� we� expect� in� average� 3� in-coming Interrupts per Interrupt line / source. Ifnone of these should be lost until Interrupt han-dling is (re-)activated, the Interrupt Buffer musthave a depth of� 3 x (max. number of Interruptsources) buffer locations.

•� � Alternatively� the Interru...