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Interface to Burst Flash Memories with Multiplexed Address and Data Bus

IP.com Disclosure Number: IPCOM000018572D
Original Publication Date: 2003-Aug-25
Included in the Prior Art Database: 2003-Aug-25
Document File: 2 page(s) / 55K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

A conventional burst flash memory (e.g. Am29BDD320) has a certain number of pins that are shown in figure 1. The chip has three basic access modes: At first there is the mode for asynchronous read. When not configured for burst mode the flash memory is accessed by a microprocessor like a normal EPROM/SRAM, i.e. using CE#, OE#, A(19-0) to select the content to be read. This content will be available at pins DQ(31-0) some nano seconds later. This access type is also used for reading miscellaneous status information from the flash memory. Next there is the synchronous burst read mode which allows fast continuous data reads. The starting address at A(19-0) is latched into the flash memory on a rising edge of CLK when ADV# is active. After a short latency the data appears at pins DQ(31-0) and in subsequent cycles the memory will automatically increment the address and provide the read data cycle by cycle. So no further addresses have to be provided by the microprocessor.

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Interface to Burst Flash Memories with Multiplexed Address and Data Bus

Idea: Tommaso Bacigalupo, DE-Muenchen

A conventional burst flash memory (e.g. Am29BDD320) has a certain number of pins that are shown in figure 1. The chip has three basic access modes:

At first there is the mode for asynchronous read. When not configured for burst mode the flash memory is accessed by a microprocessor like a normal EPROM/SRAM, i.e. using CE#, OE#, A(19-0) to select the content to be read. This content will be available at pins DQ(31-0) some nano seconds later. This access type is also used for reading miscellaneous status information from the flash memory.

Next there is the synchronous burst read mode which allows fast continuous data reads. The starting address at A(19-0) is latched into the flash memory on a rising edge of CLK when ADV# is active. After a short latency the data appears at pins DQ(31-0) and in subsequent cycles the memory will automatically increment the address and provide the read data cycle by cycle. So no further addresses have to be provided by the microprocessor.

At last there is the asynchronous write mode which is used to write to the flash memory and to configure it. The address A(19-0) is latched into the flash memory with the falling edge of WE# and the data at DQ(31-0) is latched with the rising edge of WE#.

Figure 2 shows the typical interface used between memory chip and microprocessor. The latter send the signals ADV#, A(19-0), WE# and OE# to the memory. DQ(31-0) is a bi-directional signal that can be sent by either side depending on read or write accesses being performed. WAIT# is sent by the memory to request wait states in burst mode. CLK and RESET# are system wide signals that are created somewhere else. Altogether the number of interconnections between microprocessor and memory sums up to 58 connections, which is quite much.

This invention reduces the number of interconnections by sharing the address bus with the data bus on the microprocessor side (multiplexed bus), for example by merging A(19-...