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Three-Way Transactions in Busses

IP.com Disclosure Number: IPCOM000018578D
Original Publication Date: 2003-Jul-24
Included in the Prior Art Database: 2003-Jul-24
Document File: 4 page(s) / 59K

Publishing Venue

IBM

Abstract

Three-way Transactions in Busses: A new transaction type is introduced, which combines two address transfers with one data transfer saves. In particular there are two new transfer types for reading and writing with translation. Since many busses allow multicycle data transfers (bulk transfers), the data bus can be used for other purposes in the same time. The first address transfer (from the master to the translator) can use the address path and mechanisms already present for the cache coherence operation. Overall, a higher bus bandwidth remains for other purposes and power is saved.

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Three-Way Transactions in Busses

   Typical busses provide two types of transactions, name read and write. Hence, they typically distinguish between two types of bus terminals, masters and slaves. A bus transaction is always initiated by a master, which generates an address. Either directly provided by the master or indirectly inferred by the address a particular slave is selected. In case of a read transaction data is transferred from a slave to the master, and in case of a write transactions from the master to a slave.

An extension of this mechanism is found in cache coherent busses, where some or all masters observe all or a part of the address transfers initiated by the other masters. By comparing the address with the state of an internal cache they can interfere the ongoing transactions and save modified data in their cache, invalidate an cache entry or can copy the data transferred during the reminder of the original to their cache.

In modern "systems-on-chip" there are applications where a master A does not know the final address of a read or write transaction. It needs a third unit T to provide address translation for the original address known at master A. The translation unit cannot be combined into the bus master or the slave if there are as well several bus masters and slaves affected by the service, e.g. several processors and several memories. If a separate unit is used at the bus, a redundant data transfer results when only the traditional read and write transactions were available, because two address and one data transfers are needed, but a read or write transaction combines exactly one data and one address transfer.

The process is illustrated in the following figure:

Problem: fine-grained address translation

XlateCPU

Mem

Therefore, introducing a transaction type, which combines two address transfers with one data transfer saves one data transfer over the bus. In particular there are two new transfer types for reading and writing with translation. Since many busses allow multicycle data transfers (bulk transfers), the data bus can be used for other purposes in the same time. The first address transfer (from the master to the translator) can use the address path and mechanisms already present for the cache coherence operation. Overall, a higher bus bandwidth remains for other purposes and power is saved. The new transaction pattern is illustrated in the following figure:

1

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2) Match Response

Master

1 Translater

C

Three components of the bus are used, namely the address bus (named A), the data bus (D) and the control bus C. The latter is optional and is used only for exceptional cases, e.g. when an unused table element is addressed and translation fails for this reason.

Many busses offer a control signal like bus error for this case which aborts the transaction and triggers the handling of this situation in the Master 1. When these additional transactio...