Browse Prior Art Database

Multiple Processor Interfaces for a USB Device

IP.com Disclosure Number: IPCOM000018653D
Original Publication Date: 2003-Jul-30
Included in the Prior Art Database: 2003-Jul-30
Document File: 2 page(s) / 29K

Publishing Venue

Motorola

Related People

Michael J. Mueller: AUTHOR

Abstract

In a system that supports a USB device, there can be N processors or processes that share and manage a USB device. This provides faster processing and response time on the bus and can aid in maximizing bus utilization from the device end.

This text was extracted from a Microsoft Word document.
This is the abbreviated version, containing approximately 53% of the total text.

Multiple Processor Interfaces for a USB Device

Michael J. Mueller

Abstract

In a system that supports a USB device, there can be N processors or processes that share and manage a USB device. This provides faster processing and response time on the bus and can aid in maximizing bus utilization from the device end.

In the system described herein, a USB device structure is defined and logically partitioned such that it allows two separate processes access and independent usage of the USB device. This allows separate processes to manage USB resources independently, increasing USB system throughput in the device.

Body

1.0          Overview

A Universal Serial Bus (USB) device is defined as a collection of resources that define and logically represent a system that will meet the specifications outlined by the USB specification.[1]

These resources are managed by a multiprocessing system where each process is assigned a specific set of task and resources from the collection. The processors work concurrently to perform transfers and manage device control.

The USB device contains a control endpoint, as defined by the USB specification, which is maintained and controlled by the CPU. The device also has a number of other non-control type endpoints that are physically allocated to each processor (CPU and DSP). The endpoints are logical entities that provide independent communication pipes between the device and an external USB Host controller.

The CPU and DSP do not share endpoints in this design. However, they share resources within the USB device that enable each to send transactions using their assigned endpoints. This allows each processor an independent set of registers and independent control of data being passed through the USB. This can be extended to N processors, limited only by the resources defined within the USB specification.

1.1      Communication

In this design, the CPU maintained control of the device, managing all the USB related setup and control type transactions. This allowed one processor to establish basic communication and control to the USB Host. Once established, this processor would inform other processor(s) to allow them to establish communications channels using their allocated USB resources.

The two processors in this design are loosely coupled, sharing information via common memory and semaphores.

The procedure to start communications is as foll...