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Method for sharing translation look-aside buffer entries between logical processors

IP.com Disclosure Number: IPCOM000018663D
Publication Date: 2003-Jul-30
Document File: 4 page(s) / 88K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for sharing translation look-aside buffer entries between logical processors. Benefits include improved functionality and improved performance.

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Method for sharing translation look-aside buffer entries between logical processors

Disclosed is a method for sharing translation look-aside buffer entries between logical processors. Benefits include improved functionality and improved performance.

Background

              A translation look-aside buffer (TLB) structure is provided on a CPU for storing entries that translate virtual addresses to physical addresses and for enforcing protections for each page. The TLB is an essential component of the modern computer architecture to build the virtual addressing environment. Multithreaded processor implementations have started appearing in the market and are expected to gain popularity in the future.

              Conventional multi-threading processor implementations require the TLB entries to be private to each logical processor like other processor resources, such as the register set. Multithreading processor implementations do not allow direct sharing of the TLB entries between the logical processors. Advanced processor architectures support multiple virtual regions by dividing a flat linear virtual address space to some number, designated as N, of spaces and region identifiers that are used to uniquely tag each region. The regions and the region identifiers are designed to create local, shared, and global space within a virtual address space. They eliminate the requirement for the TLB flush on a process switch.

              Even when the processor implementation/architecture supports the usage of regions, the processor implementation cannot assume that translations with the same region identifier can be shared between the logical processors. This is because that the region identifier usage varies depending upon the operating system’s policies.  Not being able to share the TLB entries between logical processors results in insufficient use of the translation entry resources in the multithreaded processor implementation and lead to a performance loss for the individual logical processor

General description

              The disclosed method is sharing translation look-aside buffer entries between logical processors when the logical processors share the same address space or regions of the address space. The method requires both the hardware implementation and the operating system support. It must ensure that the region identifiers are used to uniquely identify the usage of the region spaces, such as private to a process, shared, and global.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to enabling multiple logical processors to share the same processor resources for execution

•             Improved performance due to reducing TLB misses with the maximum use of the TLB entries between the logical processors

Detailed description

              The disclosed method enables direct sharing of the TLB entries between logical processors (see Figure 1). The disclosed method takes advantage of the fact tha...