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Method for an integrated checksum unit with a memory controller

IP.com Disclosure Number: IPCOM000018666D
Publication Date: 2003-Jul-30
Document File: 4 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an integrated checksum unit with a memory controller. Benefits include improved functionality and improved performance.

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Method for an integrated checksum unit with a memory controller

Disclosed is a method for an integrated checksum unit with a memory controller. Benefits include improved functionality and improved performance.

General description

              The disclosed method is a checksum unit integrated into a memory controller. As the memory controller performs write transactions to physical memory, the checksum unit is performing 16-bit ones-complement additions on the data being written. The result of the checksum is stored in a control and status register (CSR) in the controller, which is readable from the host CPU. The CSR is read only.

Advantages

              Some implementations of the disclosed structure and method provide one or more of the following advantages:

•             Improved functionality due to offloading TCP checksum processing to the host memory controller

•             Improved performance due to improved packet transmission speed because of offloading TCP checksum processing from the NIC

•             Improved cost effectiveness due to simplifying transmit buffer logic on the NIC

•             Improved cost effectiveness due to enabling the use of smaller NIC hardware buffers

 

Detailed description

              The checksum unit is comprised of three hardware units:

•             Set of 16 checksum CSRs

•             16-Element Content Addressable Memory (CAM)

•             16-Bit ones-complement adder

              Each CSR of the set of 16 checksum CSRs stores an independent checksum result.

              Each element of the 16-element CAM stores a 32-bit tag address field. It contains the value compared on every memory-write transaction. Each CAM entry corresponds to one of the 16 checksum result CSRs. The output of the CAM lookup is a 4-bit index, referencing one of the 16 checksum result CSRs (see Figure 1).

              The result of the 16-bit ones-complement adder is stored in one of the 16 checksum result CSRs. The CSR that the result is written to is determined by the current output of the 16 element CAM. After a result has been output by the CAM, the corresponding address tag in the CAM is incremented by 2, indicating the two bytes that have been added to the checksum calculation.

              The checksum unit typically operates so that multiple memory transactions can occur without reading and storing intermediate checksum results between transactions (see Figure 2). In the case of a cache line flush, the checksum result can be invalidated by writing a flag bit in the result CSR.  This would allow software reading the result CSR to check the integrity of any checksum result that may be stored.  It is typical to write and read network payload data to memory which has been marked as non-cacheable.  In the case of non-cacheable memory, the cache flush invalidation should never occur.  For multiprocessor memory controllers, each processor has its own checksum unit (see Figure 3). For hyperthread support, each hyperthread in each processor has its own checks...