Browse Prior Art Database

Method for the detection and correction of memory instability due to SDRAM DIMMs entering an unknown state after the assertion of reset

IP.com Disclosure Number: IPCOM000018671D
Publication Date: 2003-Jul-30
Document File: 2 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for the detection and correction of memory instability due to synchronous dynamic random access memory (SDRAM) dual inline memory modules (DIMMs) entering an unknown state after the assertion of reset. Benefits include improved reliability.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 67% of the total text.

Method for the detection and correction of memory instability due to SDRAM DIMMs entering an unknown state after the assertion of reset

Disclosed is a method for the detection and correction of memory instability due to synchronous dynamic random access memory (SDRAM) dual inline memory modules (DIMMs) entering an unknown state after the assertion of reset. Benefits include improved reliability.

Background

              System memory must be initialized on each system boot, whether powering on the system or after a reset assertion. At the assertion of reset, some DIMMs enter a state in which they do not respond to memory reads/writes, even after initialization. According to the SDRAM DIMM standards specification, performing the DIMM initialization should reset internal DIMM logic and should place the DIMMs in a good state. However, some DIMMs do not react successfully and maintain their bad state.

              The conventional mechanism for testing the system memory involves performing a simple pattern write/read comparison to various locations in memory. If the test fails, then the system is halted and an error code is displayed.

Description

              The disclosed method performs an extensive memory test that stresses all memory banks, and exercises the page empty, page hit, and page miss cases. For full coverage, CPU cache and dynamic power-down mode are enabled and disabled during the test (see Figure 1).

              The disclosed method detects the memory status using a memory t...