Browse Prior Art Database

Address Translation Using Variable -Sized Page Tables

IP.com Disclosure Number: IPCOM000018736D
Original Publication Date: 2003-Aug-04
Included in the Prior Art Database: 2003-Aug-04
Document File: 6 page(s) / 138K

Publishing Venue

IBM

Abstract

This disclosure describes the structure and implementation of a variable size page table (VSPT). Using a VSPT offers substantial performance improvements when compared to a hashed page table (HTAB) or any other fixed-size page table. VSPT can be used in any processor that supports variable size pages and software managed replacement of translation lookaside buffer (TLB) entries.

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Address Translation Using Variable -Sized Page Tables

Abstract

This disclosure describes the structure and implementation of a variable size page table (VSPT). Using a VSPT offers substantial performance improvements when compared to a hashed page table (HTAB) or any other fixed-size page table. VSPT can be used in any processor that supports variable size pages and software managed replacement of translation lookaside buffer (TLB) entries.

Introduction

In a microprocessor, the memory management unit (MMU) translates effective (logical) addresses to real (physical) addresses. All memory accesses are translated when the MMU is enabled. Translation is accomplished using a translation lookaside buffer (TLB) and page table. The TLB, implemented in hardware, stores the most recently used effective-to-physical address translations. If all valid translations cannot be contained in the TLB, or if memory translations change over time, a page table data structure which describes all valid translations is used.

If the translation of an effective address (EA) cannot be accomplished using the current valid TLB entries, the processor generates a TLB miss exception. Software handling the TLB miss exception uses the page table to locate and load proper entry into the TLB so that the translation can be retried. Memory accesses that do not cause TLB miss exceptions are several orders of magnitude faster than those that do. Using variable size TLB entries improves performance because larger amounts of memory can be translated using TLB entries, thus reducing the occurrence of TLB miss exceptions.

Address Translation Overview

Address translation is commonly used to protect programs from accessing memory that is not specifically allocated to the programs. Address translation also establishes memory with different access permissions and storage attributes.

Translated memory is divided into pages. A page is a unit of memory with address translation and storage attributes specified by a single TLB entry. Pages are aligned in memory based on their size. For example an TLB entry with 4KB page size would have a virtual address (VA) range that would start on a 4KB address boundary and would specify a real address on a 4KB boundary as well.

See Address Translation Process. illustrates typical address translation process. A 32-bit EA generated as a result of instruction execution is concatenated with the 8-bit process ID (PID) to create a 40-bit virtual address (VA). The VA is used to simultaneously search all the TLB entries. If the VA is located in the TLB, and the access is permitted, the 32-bit real address (RA) is used to access memory. If the VA is not located in the TLB, or if the access is not permitted, the processor generates an exception. The TLB miss exception is generated if the VA is not located in the TLB. TLB miss exceptions can occur during normal program execution. The protection exception is generated if the VA is located in the TLB but the...