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Organic Surface Mountable Pin Grid Array or Stud Grid Array

IP.com Disclosure Number: IPCOM000018759D
Publication Date: 2003-Aug-06
Document File: 2 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that attaches an organic Pin Grid Array (PGA) or Stud Grid Array (SGA) onto a printed circuit board (PCB). Benefits include improved reliability of a surface-mounted BGA package by reducing the overall stress in the interconnect.

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Organic Surface Mountable Pin Grid Array or Stud Grid Array

Disclosed is a method that attaches an organic Pin Grid Array (PGA) or Stud Grid Array (SGA) onto a printed circuit board (PCB). Benefits include improved reliability of a surface-mounted BGA package by reducing the overall stress in the interconnect.

Background

Currently, packages are attached to a PCB using solder balls. Due to the coefficient of thermal expansion (CTE) mismatch and different thermal expansion/contraction rates between the package and motherboard, a considerable amount of stress is built into the solder joints during surface mount.� In addition, residual stress is also present after the package surface mount and during the temp cycle.� Various interconnect failures can be associated with this stress build up, such as brittle solder joints and fatigue cracking.

General Description

The disclosed method changes the aspect ration of the interconnect by using a pin or stud to lower the cross section area-to-height ratio. Figure 1 shows how the Surface Mount Pin Grid Array (SPGA) package deforms the pins during thermal loading.� “U” is the lateral displacement that arises due the mismatch in the CTE between the substrate and motherboard.� This lateral displacement puts a shear load on the solder joints of both the SPGA and traditional BGA packages. This force scales linearly with displacement, and stiffness “K” is the scaling factor.� “K-SPGA” and “K-BGA” represent the stiffnesses of the...