Browse Prior Art Database

Method for a cache-coherent I/O domain

IP.com Disclosure Number: IPCOM000018762D
Publication Date: 2003-Aug-06
Document File: 3 page(s) / 67K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a cache-coherent input/output (I/O) domain. Benefits include improved functionality, improved performance, improved availability, and improved reliability.

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Method for a cache-coherent I/O domain

Disclosed is a method for a cache-coherent input/output (I/O) domain. Benefits include improved functionality, improved performance, improved availability, and improved reliability.

Background

        � � � � � In existing symmetric multiprocessor (SMP) architectures, multiple processors share common data structures that reside in memory. Each processor has its own cache. Coherency between these processors is maintained by explicit logic that performs the appropriate actions. For example, the logic invalidates the cache write when one processor writes to memory data that is also currently in the cache of another processor.

        � � � � � In conventional I/O subsystems, the data interaction between the I/O subsystem and the CPU is stateless. The data contained in exchanges is not interpreted for validity. States are associated with interactions between CPUs and not between I/O devices. Two NIC cards in a system do not share data.

        � � � � � Typical conventional offloaded I/O subsystems deal with raw stateless data, such as the network subsystem (which deals with frames) and the disk subsystem (which deals with sectors). I/O subsystems perform the functions of the lowest layers of the system stack. However, the trend is for these subsystems to offload upper layers of the stack so that the CPU can be freed up for increased application bandwidth. This shift makes the data exchange between the host and the offloaded subsystem a stateful interaction. One of the resulting issues is the capability to manage states among such offloaded subsystems, such as multiple NIC cards and multiple storage adapters. In not-offloaded architectures, the synchronization point is the CPU and the operating system. However, with offload architectures, synchronization must be performed outside the CPU.

General description

        � � � � � The disclosed method is a cache-coherent I/O domain that provides SMP characteristics to intelligent I/O subsystems. The method enables caching schemes and services similar to those of SMP system architectures, such as TCP/IP offload, redundancy, and high-availability features that require state management across these systems.

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Improved functionality due to enabling failover and load balancing among offloaded subsystems

•        � � � � Improved performance due to improved sys...