Browse Prior Art Database

Clock Tree Skew Fixing Algorithm

IP.com Disclosure Number: IPCOM000018876D
Original Publication Date: 2003-Aug-19
Included in the Prior Art Database: 2003-Aug-19
Document File: 6 page(s) / 112K

Publishing Venue

Motorola

Related People

Colin MacDonald: AUTHOR [+2]

Abstract

Today’s Systems on Chip(SoC) integrated circuits (ICs) have a vast number of synchronous elements requiring clocking signals. The distribution of a clock signal to a large number of endpoints is typically accomplished through the construction of a clock tree network. Clock Tree Synthesis (CTS) and Optimization (CTO) tools are used to build clock trees according to supplied constraints such as clock insertion delay and maximum clock skew. Global clock skew is the largest time difference between the arrival times of active clock edges at any two endpoints on the clock tree. However, due to a number of different factors, it’s commonly not possible for the CTS/CTO tools to meet global clock skew targets. This article describes the incentives and difficulties in managing clock skew, and describes a Clock Tree Skew Fixing Algorithm [CTSFA] and methodology for meeting clock skew goals with a minimum number of changes to the original clock tree network.

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Clock Tree Skew Fixing Algorithm

Authors: Colin MacDonald, Anis Jarrar

Abstract

Today’s Systems on Chip(SoC)  integrated circuits (ICs) have a vast number of synchronous elements requiring clocking signals. The distribution of a clock signal to a large number of  endpoints is typically  accomplished through the construction of a clock tree network. Clock Tree Synthesis (CTS) and Optimization (CTO) tools are used to build clock trees according to supplied constraints such as clock insertion delay and maximum clock skew. Global clock skew is the largest time difference between the arrival times of active clock edges at any two endpoints on the clock tree. However, due to a number of different factors, it’s commonly not possible for the CTS/CTO tools to meet global clock skew targets. This article describes the incentives and difficulties in managing clock skew, and describes a Clock Tree Skew Fixing Algorithm [CTSFA] and methodology for meeting clock skew goals with a minimum number of changes to the original  clock tree network.

Managing Clock Skew

The advance of process technology in the last few years has given designers integration capabilities never possible before and has led to a new wave of complex Systems on Chips (SoCs). These chips now include a variety of low and high-speed communication devices, volatile and non-volatile memory, analog and RF capabilities.

The advent of these new devices and the new requirements for low power operation like clock gating often leads to timing complexities that if not addressed early in the design cycle can lead to delayed schedules and to Silicon that's dead-on-arrival. Managing clock skew is one of the most critical activities in achieving timing closure in the modern flow. As on chip frequencies increase, clock skew becomes a more significant part of the available clock period and starts eating away at the performance of the most critical path in a given circuit. Reducing it provides the necessary margin in  most cases for chips to operate at the worst-case process, voltage and temperature corner.

Reducing clock skew is not just a performance issue, it is also a manufacturing issue. Scan based testing, which is currently the most popular way to structurally test chips for manufacturing defects, requires minimum skew to allow the error free shifting of scan vectors to detect stuck-at and delay faults in a circuit. Hold failures at the best-case PVT Corner is not uncommon of these circuits since there are typically no logic gates between the output of one flop and the scan input on the next flop on the scan chain. Managing and reducing clock skew in this case often resolves these hold failures.

Post CTS Skew Fixing Algorithm Introduction

The CTSFA not only provides a way of improving clock skew but does so in a very efficient manner. It finds a "minimum" fix solution that often involves only a few cells in a circuit that may contain thousands of flip-flops. Minimizing the amount of changes requir...