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Recovery Scheme in a Dual/Replicated Cache Using Parity

IP.com Disclosure Number: IPCOM000018904D
Publication Date: 2003-Aug-20
Document File: 2 page(s) / 35K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables overlay error protection, and attempts to minimize bandwidth area at only the cost of parity on the cache lines.

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Recovery Scheme in a Dual/Replicated Cache Using Parity

Disclosed is a method that enables overlay error protection, and attempts to minimize bandwidth area at only the cost of parity on the cache lines.

Background

When implementing write-back caches, data must be protected against “soft” errors (i.e. corruption due to external phenomena such as alpha particles) as the cache holds unique data that is part of the system architectural state. One way of protecting data is through, Error Correction Codes (ECC); however ECC are costly and slow.

General Description

In the case of a write-back cache that needs to offer two simultaneous random read accesses, the disclosed method replicates two single-ported caches rather than multi-porting a single cache. The two caches are completely synchronous, i.e. they contain the exact same data at any time. By doing so, error protection is guaranteed. To provide error detection, parity information is added to each line of the caches. When a read access is performed on one of the cache arrays, the parity information is retrieved to check if any bit has switched. If an error (i.e. switch) is detected, a recovery mechanism reads the correct line from the other cache array to provide the correct data.

Advantages

The disclosed method enables overlay error protection and minimizes the bandwidth area.

Figure 1.

Disclosed anonymously