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Method for a semiconductor package with a compliant interconnect layer

IP.com Disclosure Number: IPCOM000018915D
Publication Date: 2003-Aug-20
Document File: 2 page(s) / 62K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a semiconductor package with a compliant interconnect layer. Benefits include improved reliability.

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Method for a semiconductor package with a compliant interconnect layer

Disclosed is a method for a semiconductor package with a compliant interconnect layer. Benefits include improved reliability.

Background

Coefficient of thermal expansion (CTE) mismatch can occur between the semiconductor package and the die and between the semiconductor and the printed wiring board (PWB) on which the semiconductor package is assembled. The stresses generated by the CTE mismatch are absorbed by the compliant dielectric layer used to form to the outermost layers of the semiconductor package.

         Conventionally, CTE-mismatch stresses are reduced by using compliant solders and underfill polymers. However, the inner-layer dielectrics used for semiconductor device manufacturing have much less mechanical strength. The compliancy of the solder and the underfill are no longer adequate by themselves to sufficiently reduce the stress.

         CTE-mismatch stress causes delamination and cracking, which lead to solder joint, package, and device failure.

General description

The disclosed method is a semiconductor package with a compliant interconnect layer. A compliant, mechanical-energy absorbing dielectric layer is added to the die-attach side and/or to the ball grid array (BGA) side of a semiconductor package. As a result, the stresses generated by the CTE mismatch are absorbed and not transmitted to the die or PWB through the attaching solder balls.

The disclosed method includes the fabrication of the outermos...