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A Parallel Randomizer that Avoids Using Fast Bit Clock

IP.com Disclosure Number: IPCOM000019043D
Publication Date: 2003-Aug-27
Document File: 3 page(s) / 113K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a parallel randomizer, or scrambler, to simplify the circuit by avoiding parallel-to-serial conversion at the input and the inverse conversion at the output.

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A Parallel Randomizer that Avoids Using Fast Bit Clock

Disclosed is a method that uses a parallel randomizer, or scrambler, to simplify the circuit by avoiding parallel-to-serial conversion at the input and the inverse conversion at the output.

General Description

At initialization, a programmable scrambler seed (scrambler_seed[14:0]) is loaded into register lfsr[14:0]. Then during the scrambling operation, output data is computed by EXLUSIVE-ORing, the input data data_in[7:0] and least significant byte lfsr[7:0] of the register output. Simultaneously, all the 15 bits register output is fed back to update the register value
(see Figure 1).

Note. The particular scrambler used for illustration here is specified in the DOCSIS RFI spec. However, the disclosed method can be applied to any digital scramblers. It can also be used for implementing some parallel convolutional encoders.

The register update is determined by the combinatorial circuit (i.e. cloud) at the input of register lfsr[14:0]. This combinatorial circuit is specified in Figure 2 for the polynomial used: X15 + X14 + 1. The adders in the figure are binary adders or exclusive OR gates.

The circuit connection is derived from the polynomial specification of the scrambler. For the above example, the polynomial is X15 + X14 + 1 and the following steps are taken to determine the circuit connection:

Step 1. Construct an 15 by 15 matrix A as follows:

,

where

is a row vector [g1,g2,…,g14] containing the coefficients of X, X2, …, X14 terms in the polynomial;

g15 is the coefficient of X15 term in the polynomial;

is a 14 by 14 identity matrix;

is a 14 by 1 column vector of all zeros.

For our example, = [0 0 0 0 0 0 0 0 0 0 0 0 0 1] and g15=1.

Step 2. Compute B = A8 using binary arithmetic. Then B specifies connection needed for updating the register. Each flip-flop in the register is updated by a binary sum of the output of other flip-flops. If (i,j) entry in B is 1, then output of flip-flop (j-1) is used in the binary sum for updating...