Browse Prior Art Database

Method for a decoupling capacitor using a multiface terminal

IP.com Disclosure Number: IPCOM000019053D
Publication Date: 2003-Aug-27
Document File: 4 page(s) / 220K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a decoupling capacitor using a multiface terminal. Benefits include improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Method for a decoupling capacitor using a multiface terminal

Disclosed is a method for a decoupling capacitor using a multiface terminal. Benefits include improved performance.

Background

         Actual capacitors have parasitics and are not a pure capacitor. The parasitic effects of a multilayer capacitor consist of an equivalent series resistance (ESR) and an equivalent series inductance (ESL), which must be minimized to enhance power delivery performance.

         Conventionally, typical chip capacitors have multiple layers of plates stacked either vertically or side by side. The total capacitance value increases linearly as the number of layers increase. The side-by-side configuration has better performance than vertical stacks. The current injected into plates can be divided uniformly while the vertical stack may have current idle at the bottom plates, which results in ESL and ESR (see Figure 1).

         The capacitance value is determined by the spacing between the plates, dielectric permittivity, and the effective area of the plates. Most capacitor vendors have already optimized the combination of the design parameters, such as stacking plates to increase the effective area, so the performance of capacitor itself is hard to improve. However, most capacitors have resonance problems as the frequency gets higher due to the parasitics in packaging.

General description

         The disclosed method is a multilayer capacitor that reduces its own ESR and ESL

for high-quality power delivery.

         The key elements of the method include:

•         Placement of one capacitor terminal on the bottom face of the capacitor for a minimum current path

•         Use of five faces for a second terminal to increase the current paths

•         Reduction of lead ESR and ESL by using a multiple-face terminal

Advantages

         The disclosed method provides advantages, including:

•         Improved performance due to establishing a minimum current path length and low inductance from the capacitor to the la...