Browse Prior Art Database

Using Coherence Checking In A Multi-Ported Memory Controller To Insure Data Integrity

IP.com Disclosure Number: IPCOM000019262D
Original Publication Date: 2003-Sep-08
Included in the Prior Art Database: 2003-Sep-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Abstract

Disclosed is a design for using coherence checking in a multi-ported memory controller to insure data integrity.

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This is the abbreviated version, containing approximately 52% of the total text.

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  Using Coherence Checking In A Multi-Ported Memory Controller To Insure Data Integrity

  Disclosed is a technique which incorporates hardware memory coherence checking to insure data integrity in a multi-ported memory controller design. The memory controller has posted write First In First Out (FIFO) buffers on each port to improve throughput --- certainly a standard practice. These FIFOs provide a temporary repository for write data for a port while the memory is being accessed from another port. However , It is possible that once a master has posted its data into one of these FIFOs, it can subsequently initiate the reading of that data just written by a master from another port. Since the access is from another port, there is no absolute guarantee that the data transfer from the posted write FIFO into the memory array will complete prior to the initiation of the read transfer. That being the case, it is possible that the read operation will return "stale" data --- i.e. the data prior to the update --- when it is expected and required that the updated data be returned. The hardware coherence checking of this design prevents a read access from any port when it is possible that the targeted data of that access may still be located in any of the posted write FIFOs leading to the memory array.

This design blocks a read operation whenever it is possible that any of the data being accessed could still be located in any of the posted write FIFOs leading to the memory array. This is done based on the results of two comparisons. First, the requested read address is added to the requested read burst length and the result is then compared to see if it is greater than or equal to a currently active write address on another port (note that any write that has been posted to its write FIFO, but not yet completely written to the memory array is...