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Low Plasma Power TiN Deposition for Low Leakage Antifuses

IP.com Disclosure Number: IPCOM000019288D
Publication Date: 2003-Sep-09
Document File: 5 page(s) / 144K

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The IP.com Prior Art Database

Related People

S. Brad Herner: AUTHOR

Abstract

Titanium nitride deposited over a thin oxide in semiconductor devices by sputter deposition may damage the oxide, impacting device performance. Use of low plasma power during deposition prevents such damage.

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MATRIX INVENTION DISCLOSURE FORM

Short Title: Low plasma power TiN deposition for low leakage antifuses

Prepared by: S. Brad Herner

For electronic memory devices in which a bit is distinguished as programmed or unprogrammed by the value of the current passing through the device, it is advantageous for the difference between these two states to be as large as possible. For one time programmable memories based on the rupture of dielectric antifuses, this difference is current before dielectric breakdown and after dielectric breakdown. Specifically, for one time programmable memories that have a diode and antifuse in series, this difference is described as the forward unprogrammed current (IFU) and forward programmed current (IFP).

For the structure shown below, I have developed TiN deposition conditions that result in a smaller IFU value (by over 2 orders of magnitude) for a given dielectric thickness without affecting the IFP value. This by itself results in a greater difference between IFU and IFP.

The IFP value is affected by the initial dielectric thickness. As the dielectric thickness is decreased, the IFP value increases. However, the IFU also increases as the dielectric thickness is decreased. An indirect benefit of this technique to reduce the IFU value by special TiN deposition conditions is that it then allows a thinner dielectric to be used, which increases IFP. Thinner dielectrics can also be programmed faster, giving an advantage in the speed in which information can be written to the bits.

A possible secondary application of the process disclosed herein is for the manufacture of MOS transistors where a TiN “gate” is deposited on a very thin dielectric (e.g. “gate oxide”). It has been noted by previous researchers that the same process described herein, namely low plasma power sputtered TiN, can produce the same effect on thin single crystal gate oxides – namely low “leakage” current. For example, see

S. Youn, K. Roh, S. Yang, Y. Roh, K.-S. Kim, Y.-C. Jang, and N.-E. Lee, J. Vac. Sci. Tech. A 19, 1591 (2001).

We have determined a TiN deposition process for the film stack Si/SiO2/TiN/W that produces lower IFU (or leakage current) than the standard deposition process. By reducing the plasma power during sputter deposition of TiN, damage to the SiO2 substrate is reduced. While a lower plasma power reduces the TiN deposition rate considerably, this is a secondary consideration, and a small penalty compared to the large gain in device performance.

We describe the specific method of TiN deposition that produced low IFU values and compare the performance vs. the standard method of TiN deposition.

Figure 1 shows the device in which the IFU value was measured, basically consisting of a vertical Si pn diode, an SiO2 antifuse, and two TiN/W wires connecting the terminals of the diode. Several instances of th...