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Method for anticipating the zero result of an ADD operation

IP.com Disclosure Number: IPCOM000019310D
Publication Date: 2003-Sep-10
Document File: 3 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for anticipating the zero result of an ADD operation. Benefits include improved performance.

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Method for anticipating the zero result of an ADD operation

Disclosed is a method for anticipating the zero result of an ADD operation. Benefits include improved performance.

General description

         The disclosed method is the anticipation of the zero result of an ADD operation without waiting for the completion of carry propagation. The anticipation of the zero result proceeds in parallel with the ADD operation and does not wait for the carry propagation steps to complete. This procedure reduces the computation time, which results in faster throughput.

Advantages

         The disclosed method provides advantages, including:
•         Improved performance due to faster throughput because of reduced computation time

•         Improved performance due to processing in parallel with the ADD operation without waiting for the carry propagation steps to complete

Detailed description

         The disclosed method includes a circuit and an algorithm. One implementation of the circuit is depicted (see Figure 1).

         The algorithm can be described using an example. Consider two 32-bit operands, A and B. At each bit position (ith bit) of an adder. A carry is generated out of ith bit if both of the following statements are true:
A[i] = B[i] = 1; Generate = G[i] = 1

         The incoming carry to the ith bit is propagated to (i+1)th bit if both of the following statements are true:

(A[i] xor B[i]) =1; Propagate = P[i] =1

         The incoming carry is stopped (KILLed) if both of the following statements are true:

A[i] = B[i] = 0; Kill = K[i] =1

         The algorithm described below makes use of these three terms to anticipate the zero result of an ADD operation:...