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Method for a PLL clock compensator for PCI-X risers

IP.com Disclosure Number: IPCOM000019326D
Publication Date: 2003-Sep-10
Document File: 4 page(s) / 367K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a phase-locked loop (PLL) clock compensator for PCI-X risers. Benefits include improved functionality and improved performance.

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Method for a PLL clock compensator for PCI-X risers

Disclosed is a method for a phase-locked loop (PLL) clock compensator for PCI-X risers. Benefits include improved functionality and improved performance.

Background

         When a PCI-X bus is routed to a connector/slot that is intended to be used for an add-in card, length matching is required. A timing relationship must exist between the clock for the connector/slot and the clock that is routed back to the input/output (I/O) PLL. If a riser card is added to the connector/slot for 1U or 2U, (1U equaling 1 system unit of measure which is 1.75”, 2U equaling 2 units or 3.5”), chassis configurations, the clock route length on the riser breaks the timing relationship (see Figure 1).

         To solve this problem, approximately half of the line length added by the riser must be added to the clock line routed back to the I/O PLL. However, this solution reduces timing margins. The bus speed can be reduced to increase the margins so the bus works. This solution can reduce the timing margin of the platform even when a riser is not used.

         Alternatively, capacitors can be added to the clock line routed back to the I/O PLL of that PCI-X device in an attempt to adjust timing and preserve some margin. This solution causes the platform to be manufactured specifically for a riser or for no riser.

         The conventional lack of compensation for risers results in reduced timing margins or reduced performance.

Description

         The disclosed method is a phase-locked loop (PLL) clock compensator for PCI-X risers. A single connector/slot uses two general purpose I/O (GPIO) lines from the device to the reserved or unused pins of the connector/slot in a resister pull-up/pull-down riser detection scheme. When the riser type is detected, other signals from the device are routed to a programmable delay device. It programs the device to add the appropriate amount of delay to the clock line routed back to the I/O PLL. The delay compensates for the additional line length added to the clock line routed to the connector/slot by the insertion of a riser (see Figure 2). When a riser is not present, the incoming GPIO detects no riser and the outgoing GPIO deactivates the delay. For example, the length of Clk 6-to-PLL in time is 1000 ps, which is the same as the Clk # to the PCI-X slot. When a riser is present, the incoming GPIO detects a riser an...