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Read Stability Test Enhancement for ASIC SRAM

IP.com Disclosure Number: IPCOM000019503D
Original Publication Date: 2003-Sep-17
Included in the Prior Art Database: 2003-Sep-17
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Abstract

Read stability testing is becoming increasingly more critical for CMOS SRAMs. An SRAM design feature, which allows for more robust read stability testing, is presented in this article.

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Read Stability Test Enhancement for ASIC SRAM

   Read stability testing is performed on SRAMs, to detect faulty cells that erroneously change their logic states during a read operation. This article addresses marginal memory cells - cells that may pass read stability testing but subsequently fail in a customer's application.

     A known technique for detecting such marginal cells is to hold the SRAM's bitline pre-charge on during the read stability "disturb" patterns. This increases the potential for flipping the state of the cell during a read operation. In some SRAM designs, however, the bitline precharge is held on for unselected bitlines along the selected wordline, during normal operation. In this case, the read stability test provides no additional margin, relative to the normal mode of operation. Hence, marginal cells that pass the test could fail in the customer's application.

     To provide a more robust read stability test, for SRAMs that maintain the bitline precharge for unselected bitlines along a selected wordline, the bitline precharge devices are strengthened during the read stability test's "disturb" patterns. A lower impedance to VDD on the bitlines increases the potential for disturbing memory cells. As such, this essentially provides read stability design margin, relative to the normal mode of operation (i.e., normal precharge devices). The read stability test is more likely to detect marginal cells that could otherwise fail in the customer's application...