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Method for aggressive clock gating for signals that cannot be gated

IP.com Disclosure Number: IPCOM000019513D
Publication Date: 2003-Sep-17
Document File: 3 page(s) / 63K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for aggressive clock gating for signals that cannot be gated. Benefits include improved power performance and improved design simplicity.

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Method for aggressive clock gating for signals that cannot be gated

Disclosed is a method for aggressive clock gating for signals that cannot be gated. Benefits include improved power performance and improved design simplicity.

Background

In conventional design methodologies, one of the best ways to save power is to turn off the clocks to logic blocks. This saves significant power because the clock network is no longer charging and discharging. Additionally, latches and flip-flops no longer force signals to charge and discharge. For example, if no micro-operation (uop) is valid, the flop-flops containing the address bits can maintain the old address without the clock being active during the cycle of inactivity. The address signals remain valid for multiple cycles even though the uop corresponding to this address is only valid for the one cycle. Only when a new address enters into that pipeline stage is the clock required to toggle, enabling the state element to capture the new data (see Figure 1).

         However, for special signals, conventional design methodologies for power savings are inadequate. An example is the first signal for tracking the validity of a micro-operation. The first signal cannot be on a 1-cycle clock because the first signal in the following stage remains high for multiple cycles. The processor detects valid uops, which is incorrect and causes multiple logic failures. The conventional solution is example 1, moving the first signal to a free running clock. Howe...