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Method for a low latency design for cache with multiple cycle access time

IP.com Disclosure Number: IPCOM000019514D
Publication Date: 2003-Sep-17
Document File: 2 page(s) / 73K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a low latency design for cache with multiple cycle access time. Benefits include improved performance and improved design flexibility.

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Method for a low latency design for cache with multiple cycle access time

Disclosed is a method for a low latency design for cache with multiple cycle access time. Benefits include improved performance and improved design flexibility.

Background

         A high-level cache (level-3 and above) typically has a large capacity but low utilization because the request is fulfilled by the lower level caches a majority of the time. Tag lookup requires multiple cycles. Data access requires a greater number of cycles. The look-up time must account for sending request information to a large area and getting back the results. Many tag lookups involve at least 1 cycle for flight time, and data lookups involve multiple cycles for flight time.

         Conventional design theory includes the concept that the latency observed by all the accesses should be uniform.

General description

         The disclosed method is a cache design that reduces the overall latency of the data pipeline of a high-level cache. The key elements of the method include:

•         Multistage cache design

•         Requested accesses typically end up in the faster cache section

•         Tag lookup for stage B is performed in parallel with the stage-A lookup, though stage-A lookup results may arrive earlier

•         Cycles that are spent in the tag and data migration are hidden due to the low utilization of the high-level cache

Advantages

         The disclosed method provides advantages, including:

•         Improved performance due to improved response (reduced latency) to a subset of requests because the cache is organized in two or more sections

•         Improved design flexibility due to the capability to be generalized into multiple sections

Detailed description

         The disclosed method includes adata pipeline with lower latency. To keep tag and data access latency lower, the cache is a multistage cache. Let the cache be a k-way cache, where k=m+n. The first stage cache consists of 2s sets of m ways. The second stage consist of 2s sets of n ways each. The number m is significantly smaller than n. Cache management tries to migrate accesses that are more likely to be accessed again to the faster section of the cache. The tag lookup for stage B is performed in parallel with the stage-A lookup. The stage-A lookup results may arrive earlier (see Figure 1).

         The following three outcomes to a tag/data lookup are possible:

•         Stage-A hit, stage-...