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Single ended/Differential line monitoring and auto matching

IP.com Disclosure Number: IPCOM000019682D
Published in the IP.com Journal: Volume 3 Issue 10 (2003-10-25)
Included in the Prior Art Database: 2003-Oct-25
Document File: 3 page(s) / 97K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Signal edge rates define the transition point from normal traces to transmission lines and are important for transferring information. As CPU (Central Processing Unit) frequencies increase to allow faster data rates, edge rates become faster which worsens the transmission line effects. One kind of those effects are reflections which appear when a signal encounters a mismatch in impedance. This mismatch can be the result of trace geometry, capacitive loading or improperly terminated traces. Up to now there are several well known solutions like the series source resistor, AC termination, parallel termination or Thevenin termination. All of these methods may work well in certain cases but resistor and capacitor values always have to be predetermined and then are fixed. There will be no automatic tuning so they cannot react to temperature changes and variation of traces on different PCB bards. A tunable solution has been proposed in US patent 5,726,583 but it still has a number of disadvantages. First the user has to know the line impedance and enable a number of parallel elements. He also has to program the elements as they do not adjust themselves to changes of the impedance. Additionally the circuit is not very accurate and becomes more complex if the line impedance is low.

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© SIEMENS AG 2003 file: ifx_2003J52815.doc page: 1

Single ended/Differential line monitoring and auto matching

Idea: Ban Hok Goh, SG-Singapore

Signal edge rates define the transition point from normal traces to transmission lines and are important for transferring information. As CPU (Central Processing Unit) frequencies increase to allow faster data rates, edge rates become faster which worsens the transmission line effects. One kind of those effects are reflections which appear when a signal encounters a mismatch in impedance. This mismatch can be the result of trace geometry, capacitive loading or improperly terminated traces.

Up to now there are several well known solutions like the series source resistor, AC termination, parallel termination or Thevenin termination. All of these methods may work well in certain cases but resistor and capacitor values always have to be predetermined and then are fixed. There will be no automatic tuning so they cannot react to temperature changes and variation of traces on different PCB bards. A tunable solution has been proposed in US patent 5,726,583 but it still has a number of disadvantages. First the user has to know the line impedance and enable a number of parallel elements. He also has to program the elements as they do not adjust themselves to changes of the impedance. Additionally the circuit is not very accurate and becomes more complex if the line impedance is low.

The idea proposed herewith describes a circuit that monitors the signal on the line and automatically tunes itself to match the impedance on the receiver side so the transmission line will be properly terminated and reflection becomes negligible or is at least greatly reduced. For example if the line impedance is designed to be 50 Ohm, but later due to tolerances turns out to be 55 Ohm, the line impedance is sensed by the line impedance circuit. It will then adjust the load impedance's current and tune the load impedance to 55 Ohm to match the line impedance.

As the block diagram 1 shows the signal is monitored on the receiver side where the voltages are compared against a predetermined value representing the matching impedance value. Thresholds can be set to define a certain tolerance, e.g. 5%. If the compare shows differences smaller than this tolerance the impedance matching is within limits and nothing happens. If on the other hand the difference exceeds the set limit the circuit will then adjust the impedance on the receiver side based on the received input signal. The whole circuit is shown in figure 1. It is for a single ended clock driver or differential clock driver. It has a positive and a negative line. If there is a single ended signal the positive line A is used. If there is a differential line the complementary negative line B is also needed.

In the positive line circuit the operational amplifiers Op1 and Op2 are used as the comparator gating window. The upper threshold (defined by the tolerance) is set by...